전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

74AUP1G32GF 데이터시트(PDF) 10 Page - NXP Semiconductors

부품명 74AUP1G32GF
상세설명  Low-power 2-input OR-gate
Download  21 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  NXP [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo NXP - NXP Semiconductors

74AUP1G32GF 데이터시트(HTML) 10 Page - NXP Semiconductors

Back Button 74AUP1G32GF Datasheet HTML 6Page - NXP Semiconductors 74AUP1G32GF Datasheet HTML 7Page - NXP Semiconductors 74AUP1G32GF Datasheet HTML 8Page - NXP Semiconductors 74AUP1G32GF Datasheet HTML 9Page - NXP Semiconductors 74AUP1G32GF Datasheet HTML 10Page - NXP Semiconductors 74AUP1G32GF Datasheet HTML 11Page - NXP Semiconductors 74AUP1G32GF Datasheet HTML 12Page - NXP Semiconductors 74AUP1G32GF Datasheet HTML 13Page - NXP Semiconductors 74AUP1G32GF Datasheet HTML 14Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 21 page
background image
74AUP1G32
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 7 — 8 July 2013
10 of 21
NXP Semiconductors
74AUP1G32
Low-power 2-input OR-gate
[1]
tpd is the same as tPLH and tPHL.
12. Waveforms
CL = 15 pF
tpd
propagation delay
A, B to Y; see Figure 8
[1]
VCC = 1.1 V to 1.3 V
3.0
15.6
3.0
17.2
ns
VCC = 1.4 V to 1.6 V
2.0
9.8
2.0
10.8
ns
VCC = 1.65 V to 1.95 V
1.8
7.9
1.8
8.7
ns
VCC = 2.3 V to 2.7 V
1.6
6.3
1.6
6.9
ns
VCC = 3.0 V to 3.6 V
1.5
5.8
1.5
6.4
ns
CL = 30 pF
tpd
propagation delay
A, B to Y; see Figure 8
[1]
VCC = 1.1 V to 1.3 V
4.0
21.5
4.0
23.7
ns
VCC = 1.4 V to 1.6 V
2.9
13.3
2.9
14.7
ns
VCC = 1.65 V to 1.95 V
2.4
10.7
2.4
11.8
ns
VCC = 2.3 V to 2.7 V
2.2
8.4
2.2
9.3
ns
VCC = 3.0 V to 3.6 V
2.1
7.7
2.1
8.5
ns
Table 9.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9
Symbol
Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Max
Min
Max
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage drop that occur with the output load.
Fig 8.
The data input (A or B) to output (Y) propagation delays
mna615
tPHL
tPLH
VM
VM
A, B input
Y output
GND
VI
VOH
VOL
Table 10.
Measurement points
Supply voltage
Output
Input
VCC
VM
VM
VI
tr = tf
0.8 V to 3.6 V
0.5
 V
CC
0.5
 V
CC
VCC
 3.0 ns


유사한 부품 번호 - 74AUP1G32GF

제조업체부품명데이터시트상세설명
logo
NXP Semiconductors
74AUP1G32GM PHILIPS-74AUP1G32GM Datasheet
83Kb / 16P
   Low-power 2-input OR gate
Rev. 01-2 August 2005
logo
Nexperia B.V. All right...
74AUP1G32GM NEXPERIA-74AUP1G32GM Datasheet
273Kb / 18P
   Low-power 2-input OR-gate
Rev. 11 - 17 January 2022
74AUP1G32GM-Q100 NEXPERIA-74AUP1G32GM-Q100 Datasheet
227Kb / 14P
   Low-power 2-input OR-gate
74AUP1G32GN NEXPERIA-74AUP1G32GN Datasheet
273Kb / 18P
   Low-power 2-input OR-gate
Rev. 11 - 17 January 2022
74AUP1G32GS NEXPERIA-74AUP1G32GS Datasheet
273Kb / 18P
   Low-power 2-input OR-gate
Rev. 11 - 17 January 2022
More results

유사한 설명 - 74AUP1G32GF

제조업체부품명데이터시트상세설명
logo
NXP Semiconductors
74AUP1G32 PHILIPS-74AUP1G32 Datasheet
83Kb / 16P
   Low-power 2-input OR gate
Rev. 01-2 August 2005
logo
Nexperia B.V. All right...
74AUP1G32 NEXPERIA-74AUP1G32 Datasheet
273Kb / 18P
   Low-power 2-input OR-gate
Rev. 11 - 17 January 2022
74AXP1G32 NEXPERIA-74AXP1G32 Datasheet
797Kb / 17P
   Low-power 2-input OR gate
74AUP1G32-Q100 NEXPERIA-74AUP1G32-Q100 Datasheet
227Kb / 14P
   Low-power 2-input OR-gate
logo
NXP Semiconductors
74AUP2G32 NXP-74AUP2G32 Datasheet
100Kb / 17P
   Low-power dual 2-input OR gate
Rev. 03-8 January 2009
logo
Nexperia B.V. All right...
74AUP2G32 NEXPERIA-74AUP2G32 Datasheet
302Kb / 20P
   Low-power dual 2-input OR gate
Rev. 9 - 24 June 2022
74AXP1G86 NEXPERIA-74AXP1G86 Datasheet
835Kb / 17P
   Low-power 2-input EXCLUSIVE-OR gate
logo
NXP Semiconductors
74AUP1G86 PHILIPS-74AUP1G86 Datasheet
67Kb / 17P
   Low-power 2-input EXCLUSIVE-OR gate
Rev. 02.00-16 May 2006
logo
Nexperia B.V. All right...
74AUP1G86-Q100 NEXPERIA-74AUP1G86-Q100 Datasheet
222Kb / 14P
   Low-power 2-input EXCLUSIVE-OR gate
74AUP1G86 NEXPERIA-74AUP1G86 Datasheet
274Kb / 18P
   Low-power 2-input EXCLUSIVE-OR gate
Rev. 8 - 24 January 2022
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21


데이터시트 다운로드

Go To PDF Page


링크 URL




개인정보취급방침
ALLDATASHEET.CO.KR
ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com