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74AUP1G32GF 데이터시트(PDF) 10 Page - NXP Semiconductors |
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74AUP1G32GF 데이터시트(HTML) 10 Page - NXP Semiconductors |
10 / 21 page 74AUP1G32 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 7 — 8 July 2013 10 of 21 NXP Semiconductors 74AUP1G32 Low-power 2-input OR-gate [1] tpd is the same as tPLH and tPHL. 12. Waveforms CL = 15 pF tpd propagation delay A, B to Y; see Figure 8 [1] VCC = 1.1 V to 1.3 V 3.0 15.6 3.0 17.2 ns VCC = 1.4 V to 1.6 V 2.0 9.8 2.0 10.8 ns VCC = 1.65 V to 1.95 V 1.8 7.9 1.8 8.7 ns VCC = 2.3 V to 2.7 V 1.6 6.3 1.6 6.9 ns VCC = 3.0 V to 3.6 V 1.5 5.8 1.5 6.4 ns CL = 30 pF tpd propagation delay A, B to Y; see Figure 8 [1] VCC = 1.1 V to 1.3 V 4.0 21.5 4.0 23.7 ns VCC = 1.4 V to 1.6 V 2.9 13.3 2.9 14.7 ns VCC = 1.65 V to 1.95 V 2.4 10.7 2.4 11.8 ns VCC = 2.3 V to 2.7 V 2.2 8.4 2.2 9.3 ns VCC = 3.0 V to 3.6 V 2.1 7.7 2.1 8.5 ns Table 9. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9 Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Max Min Max Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage drop that occur with the output load. Fig 8. The data input (A or B) to output (Y) propagation delays mna615 tPHL tPLH VM VM A, B input Y output GND VI VOH VOL Table 10. Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 0.8 V to 3.6 V 0.5 V CC 0.5 V CC VCC 3.0 ns |
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