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CDC7005RGZR 데이터시트(PDF) 11 Page - Texas Instruments |
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CDC7005RGZR 데이터시트(HTML) 11 Page - Texas Instruments |
11 / 34 page CDC7005 3.3V HIGH PERFORMANCE CLOCK SYNTHESIZER AND JITTER CLEANER SCAS685L− DECEMBER 2002 − REVISED JUNE 2009 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional description of the logic (continued) Table 11. MUX0, MUX1, MUX2, MUX3, and MUX4 Selection MUX2 MUX1 MUX0 SELECTED DIVIDED VCXO SIGNAL DEFAULT 0 0 0 Div by 1 For Y0 0 0 1 Div by 2 For Y1 0 1 0 Div by 4 For Y2 0 1 1 Div by 8 For Y3 and Y4 1 0 0 Div by 16 1 0 1 Div by 8 1 1 0 Div by 8 1 1 1 Div by 8 VCC REF_IN Clock Fed Through the M Divider and Delay 0 V VCXO_IN Clock Fed Through the N Divider and Delay V(PFD1) (Internal Signal) V(PFD2) (Internal Signal) ICP (Bit 30 of Word 1 = 1, Default State) ICP (Bit 30 of Word 1 = 0) PFD Pulse Width Delay PFD Pulse Width Delay NOTE: The purpose of the PFD pulse width delay is to improve spurious suppression. (See Table 7) Figure 2. Charge Pump Current Direction |
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