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BS616UV8021 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 6 Page - Brilliance Semiconductor

๋ถ€ํ’ˆ๋ช… BS616UV8021
์ƒ์„ธ๋‚ด์šฉ  Ultra Low Power/Voltage CMOS SRAM 512K x 16 or 1M x 8 bit switchable
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BS616UV8021 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 6 Page - Brilliance Semiconductor

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Revision 2.2
April 2001
6
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to +70oC, Vcc=2.0V )
READ CYCLE
AC TEST CONDITIONS
AC TEST LOADS AND WAVEFORMS
BSI
BS616UV8021
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
โ€OFF โ€STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
BS616UV8021-70
MIN. TYP. MAX.
UNIT
Data Byte Control to Output High Z
Read Cycle Time
t
AVAX
t
AVQV
t
E1LQV
t
GLQV
t
BE
t
EHQZ
t
GHQZ
t
BDO
t
GLQX
t
ELQX
t
BA
t
RC
t
AA
t
ACS1
t
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
Address Access Time
Chip Select Access Time
Data Byte Control Access Time
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
Output Disable to Output Address Change
Data Byte Control to Output Low Z
70
10
10
10
0
0
0
10
t
AXQX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output Enable to Output Valid
(CE1)
(CE2,CE1)
70
70
70
50
50
35
30
30
BS616UV8021-10
MIN. TYP. MAX.
100
15
15
15
0
0
0
15
100
100
100
60
60
40
35
35
(CE2,CE1)
ns
t
E2LQV
t
ACS2
(CE2)
Chip Select Access Time
(LB,UB)
(LB,UB)
(LB,UB)
R0201-BS616UV8021
โ„ฆ
800
THEVENIN EQUIVALENT
ALL INPUT PULSES
โ†’
10%
90%
โ†
Vcc
GND
โ†’
โ† 5ns
90%
10%
1.2V
OUTPUT
FIGURE 2
2V
OUTPUT
INCLUDING
JIG AND
SCOPE
1333
โ„ฆ
2000
5PF
FIGURE 1B
2V
OUTPUT
INCLUDING
JIG AND
SCOPE
1333
โ„ฆ
100PF
FIGURE 1A
2000


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