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DAC712UB 데이터시트(PDF) 11 Page - Burr-Brown (TI) |
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DAC712UB 데이터시트(HTML) 11 Page - Burr-Brown (TI) |
11 / 12 page 11 ® DAC712 A0 is the enable control for the DATA INPUT LATCH. A1 is the enable for the D/A LATCH. WR is used to strobe data into latches enabled by A0, and A1. Refer to the block diagram of Figure 1 and to Timing Diagram on page 3. CLR sets the INPUT DATA LATCH to all zero and the D/A LATCH to a code that gives bipolar 0V at the D/A output. SINGLE-BUFFERED OPERATION To operate the DAC712 interface as a single-buffered latch, the DATA INPUT LATCH is permanently enabled by connecting A0 to DCOM. If A1 is not used to enable the D/A, it should be connected to DCOM also. For this mode of operation, the width of WR will need to be at least 80ns minimum to pass data through the DATA INPUT LATCH and into the D/A LATCH. TRANSPARENT INTERFACE The digital interface of the DAC712 can be made transpar- ent by asserting AO, A1, and WR LOW, and asserting CLR HIGH. For no external adjustments, pins 4 and 6 are not connected. External resistors R1 - R4 are standard ±1% values. Range of adjustment at least ±0.3% FSR. 10k Ω 3 4 6 ±10V V OUT 9.75k Ω IDAC 0-2mA ≈ +2.5V 15k Ω R 3 27k Ω R 4 10k Ω 120 Ω 180 Ω R 1 500 Ω R 2 500 Ω 5 170 Ω 250 Ω Internal +10V Reference V REF OUT Gain Adjust Bipolar Offset Adjust 2 ACOM FIGURE 6. Manual Offset and Gain Adjust Circuits. |
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유사한 설명 - DAC712UB |
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