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SN74LS221D 데이터시트(PDF) 1 Page - Motorola, Inc

부품명 SN74LS221D
상세설명  DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS
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제조업체  MOTOROLA [Motorola, Inc]
홈페이지  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

SN74LS221D 데이터시트(HTML) 1 Page - Motorola, Inc

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positive logic: Low input to clear resets Q low and
positive logic: Q high regardless of dc levels at A
positive logic: or B inputs.
14
13
12
11
10
9
1
2
3
4
5
6
7
16
15
8
VCC
1A
1 Rext/
Cext
1
Cext 1Q
2Q
2B
2
CLR
2A
1B
1
CLR
1Q
2Q
2
Cext
2 Rext/
Cext
GND
Q
Q
CLR
Q
Q
CLR
+
VCC
Rext
R/C
Cext
*See operational notes — Pulse Trigger Modes
5-380
FAST AND LS TTL DATA
DUAL MONOSTABLE
MULTIVIBRATORS
WITH SCHMITT-TRIGGER INPUTS
Each multivibrator of the LS221 features a negative-transition-triggered
input and a positive-transition-triggered input either of which can be used as
an inhibit input.
Pulse triggering occurs at a voltage level and is not related to the transition
time of the input pulse. Schmitt-trigger input circuitry for B input allows
jitter-free triggering for inputs as slow as 1 volt/ second, providing the circuit
with excellent noise immunity. A high immunity to VCC noise is also provided
by internal latching circuitry.
Once triggered, the outputs are independent of further transitions of the
inputs and are a function of the timing components. The output pulses can be
terminated by the overriding clear. Input pulse width may be of any duration
relative to the output pulse width. Output pulse width may be varied from 35
nanoseconds to a maximum of 70 s by choosing appropriate timing
components. With Rext = 2.0 kΩ and Cext = 0, a typical output pulse of 30
nanoseconds is achieved. Output rise and fall times are independent of pulse
length.
Pulse width stability is achieved through internal compensation and is
virtually independent of VCC and temperature. In most applications, pulse
stability will only be limited by the accuracy of external timing components.
Jitter-free operation is maintained over the full temperature and VCC ranges
for greater than six decades of timing capacitance (10 pF to 10
µF), and
greater than one decade of timing resistance (2.0 to 70 k
Ω for the
SN54LS221, and 2.0 to 100 k
Ω for the SN74LS221). Pulse width is defined
by the relationship: tw(out) = CextRext ln 2.0 0.7 Cext Rext; where tW is in ns
if Cext is in pF and Rext is in kΩ. If pulse cutoff is not critical, capacitance up
to 1000
µF and resistance as low as 1.4 kΩ may be used. The range of
jitter-free pulse widths is extended if VCC is 5.0 V and 25°C temperature.
SN54LS221 and SN74LS221 is a Dual Highly Stable One-Shot
Overriding Clear Terminates Output Pulse
Pin Out is Identical to SN54/74LS123
FUNCTION TABLE
(EACH MONOSTABLE)
INPUTS
OUTPUTS
CLEAR
A
B
Q
Q
L
X
X
L
H
X
H
X
L
H
X
X
L
L
H
H
L
°
H
±
H
*
°
L
H
TYPE
TYPICAL
POWER
MAXIMUM
OUTPUT PULSE
DISSIPATION
LENGTH
SN54LS221
23 mW
49 s
SN74LS221
23 mW
70 s
SN54/74LS221
DUAL MONOSTABLE
MULTIVIBRATORS
WITH SCHMITT-TRIGGER INPUTS
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN
Plastic
SN74LSXXXD
SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03


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