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CAT24C081JI-28TE13 데이터시트(PDF) 8 Page - Catalyst Semiconductor |
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CAT24C081JI-28TE13 데이터시트(HTML) 8 Page - Catalyst Semiconductor |
8 / 12 page CAT24CXX1/XX2 8 Advanced Doc. No. 25079-00 1/98 M-1 BYTE ADDRESS SLAVE ADDRESS S A C K A C K DATA A C K S T O P P BUS ACTIVITY: MASTER SDA LINE S T A R T Figure 7. Byte Write Timing Figure 8. Page Write Timing ACKNOWLEDGE After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledg- ing device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT24CXXX responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8- bit byte. When the CAT24CXXX begins a READ mode it trans- mits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this ac- knowledge, the CAT24CXXX will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. WRITE OPERATIONS Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/ W bit set to zero) to the Slave device. After t he Slave generates an acknowledge, the Master sends a 8-bit address that is to be written into the address pointers of the CAT24CXXX. After receiving another acknowledge from the Slave, the Master device trans- mits the data to be written into the addressed memory location. The CAT24CXXX acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to nonvolatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. Page Write The 24CXXX writes up to 16 bytes of data in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 15 additional bytes. After each byte has been transmitted, CAT24CXXX will respond with an acknowledge, and internally increment the lower order address bits by one. The high order bits remain un- changed. If the Master transmits more than 16 bytes before sending the STOP condition, the address counter ‘wraps around’, and previously transmitted data will be overwrit- ten. When all 16 bytes are received, and the STOP condi tion has been sent by the Master, the internal program- ming cycle begins. At this point, all received data is written to the CAT24CXXX in a single write cycle. BUS ACTIVITY: MASTER SDA LINE DATA n+15 BYTE ADDRESS (n) A C K A C K DATA n A C K S T O P S A C K DATA n+1 A C K S T A R T P SLAVE ADDRESS |
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