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AD5171BRJ50-RL7 데이터시트(PDF) 5 Page - Analog Devices |
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AD5171BRJ50-RL7 데이터시트(HTML) 5 Page - Analog Devices |
5 / 24 page AD5171 Rev. D | Page 5 of 24 TIMING CHARACTERISTICS: 5 kΩ, 10 kΩ, 50 kΩ, AND 100 kΩ VDD = 3 V to 5 V ± 10%, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted. Table 2. Parameter Symbol Conditions Min Typ1 Max Unit INTERFACE TIMING CHARACTERISTICS (APPLY TO ALL PARTS2, 3) SCL Clock Frequency fSCL 400 kHz tBUF Bus Free Time Between Start and Stop t1 1.3 μs tHD;STA Hold Time (Repeated Start) t2 After this period, the first clock pulse is generated 0.6 μs tLOW Low Period of SCL Clock t3 1.3 μs tHIGH High Period of SCL Clock t4 0.6 50 μs tSU;STA Setup Time for Start Condition t5 0.6 μs tHD;DAT Data Hold Time t6 0.9 μs tSU;DAT Data Setup Time t7 0.1 μs tF Fall Time of Both SDA and SCL Signals t8 0.3 μs tR Rise Time of Both SDA and SCL Signals t9 0.3 μs tSU;STO Setup Time for Stop Condition t10 0.6 μs OTP Program Time t11 400 ms 1 Typical specifications represent average readings at 25°C and VDD = 5 V. 2 Guaranteed by design; not subject to production test. 3 All dynamic characteristics use VDD = 5 V. SCL SDA t1 t2 t3 t8 t8 t9 t4 t5 t9 t7 t6 t10 P PS Figure 3. Interface Timing Diagram |
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