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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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CS4327 데이터시트(PDF) 8 Page - Cirrus Logic |
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CS4327 데이터시트(HTML) 8 Page - Cirrus Logic |
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8 / 36 page  CS4327 8 DS190F1 GENERAL DESCRIPTION The CS4327 is a complete stereo digital-to-analog system including digital interpolation, 128x fourth- order delta-sigma digital-to-analog conversion, and analog filtering, see Figure 2. This architecture pro- vides a high insensitivity to clock jitter. The DAC converts digital data at any input sample rate be- tween 1 and 50 kHz, including the standard audio rates of 48, 44.1 and 32 kHz. The primary purpose of using delta-sigma modula- tion techniques is to avoid the limitations of laser trimmed resistive DAC architectures by using an inherently linear 1-bit DAC. The advantages of a 1- bit DAC include: ideal differential linearity, no dis- tortion mechanisms due to resistor matching errors and no linearity drift over time and temperature due to variations in resistor values. Digital Interpolation Filter The digital interpolation filter increases the sample rate by a factor of 4 and is followed by a 32x digital sample-and-hold to effectively achieve a 128x in- terpolation filter. This filter eliminates images of the baseband audio signal which exist at multiples of the input sample rate, Fs. This allows for the se- lection of a less complex analog filter based on out- of-band noise attenuation requirements rather than anti-image filtering. Following the interpolation filter, the resulting frequency spectrum has images of the input signal at multiples of 128x the input sample rate. These images are removed by the ex- ternal analog filter. Delta-Sigma Modulator The interpolation filter is followed by a fourth-or- der delta-sigma modulator which converts the 24- bit interpolation filter output into 1-bit data at 128x Fs. Switched-Capacitor Filter The delta-sigma modulator is followed by a digital- to-analog converter which translates the 1-bit data into a series of charge packets. The magnitude of the charge in each packet is determined by sam- pling of a voltage reference onto a switched capac- itor, where the polarity of each packet is controlled by the 1-bit signal. This technique greatly reduces the sensitivity to clock jitter and is a major im- provement over earlier generations of 1-bit digital- to-analog converters where the magnitude of charge in the D-to-A process is determined by switching a current reference for a period of time defined by the master clock. SYSTEM DESIGN Master Clock The Master Clock, MCLK, is used to operate the digital interpolation filter and the delta-sigma mod- ulator. MCLK must be either 256x, 384x or 512x the desired Input Sample Rate, Fs. Fs is the fre- quency at which digital audio samples for each channel are input to the DAC and is equal to the LRCK frequency. The MCLK to LRCK frequency ratio is detected automatically during the initializa- tion sequence by counting the number of MCLK Interpolator Delta-Sigma Modulator DAC Analog Low-Pass Filter AOUT Figure 2. Block Diagram |
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