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M-88L70-01T 데이터시트(PDF) 2 Page - Clare, Inc. |
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M-88L70-01T 데이터시트(HTML) 2 Page - Clare, Inc. |
2 / 8 page www.clare.com M-88L70 Rev. 1 2 Filter The low and high group tones are separated by applying the dual-tone signal to the inputs of two 9th order switched capacitor bandpass filters with bandwidths that correspond to the bands enclosing the low and high group tones. The filter also incorporates notches at 350 and 440 Hz, providing excellent dial tone rejection. Each filter output is followed by a single-order switched capac- itor section that smoothes the signals prior to limiting. Signal limiting is performed by high-gain comparators provided with hysteresis to prevent detection of unwant- ed low-level signals and noise. The comparator outputs provide full-rail logic swings at the frequencies of the incoming tones. Decoder The M-88L70 decoder uses a digital counting technique to determine the frequencies of the limited tones and to verify that they correspond to standard DTMF frequen- cies. A complex averaging algorithm is used to protect against tone simulation by extraneous signals (such as voice) while tolerating small frequency variations. The algorithm ensures an optimum combination of immunity to talkoff and tolerance to interfering signals (third tones) and noise. When the detector recognizes the simultane- ous presence of two valid tones (known as “signal condi- tion”), it raises the Early Steering flag (ESt). Any subse- quent loss of signal condition will cause ESt to fall. Steering Circuit Before a decoded tone pair is registered, the receiver checks for a valid signal duration (referred to as “char- acter-recognition-condition”). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes V C (see Figure 3) to rise as the capacitor discharges. Provided that signal condition is maintained (ESt remains high) for the validation period (t GTP), VC reaches the threshold (VTSt) of the steering logic to register the tone pair, thus latching its corre- sponding 4-bit code (see Table 2) into the output latch. At this point, the GT output is activated and drives V C to V DD. GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the “delayed steering” output flag (StD) goes high, signaling that a received tone pair has been reg- istered. The contents of the output latch are made available on the 4-bit output bus by raising the three- state control input (OE) to a logic high. The steering cir- cuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (dropouts) too short to be consid- Table 1 Pin Functions Pin Name Description 1 IN+ Non-inverting input 2 IN -Inverting input 3 GS Gain select. Gives access to output of front-end amplifier for connection of feedback resistor. 4V REF Reference voltage output (nominally V DD/2). May be used to bias the inputs at mid-rail. 5 INH Inhibits detection of tones representing keys A, B, C, and D. This input is internally pulled down. 6 PD Power down. Logic high powers down the device and inhibits the oscillator. This input is internally pulled down. 7 OSC1 Clock input 8 OSC2 Clock output 9V SS Negative power supply (normally connected to 0 V). 10 OE Tri-state output enable (input). Logic high enables the outputs Q1 - Q4. Internal pullup. 11-14 Q1, Q2, Tri-state outputs. When enabled by OE, provides the code corresponding to the last valid tone pair received Q3, Q4 (see Table 5.) 15 StD Delayed steering output. Presents a logic high when a received tone pair has been registered and the output latch is updated. Returns to logic low when the voltage on St/GT falls below V TSt 16 ESt Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. 17 St/GT Steering input/guard time output (bidirectional). A voltage greater than V TSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than V TSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time constant, and its state is a function of ESt and the voltage on St. (See Figure 5). 18 V DD Positive power supply Connections to the front-end differential amplifier 3.579545 MHz crystal connected between these pins completes internal oscillator. |
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