Data/Tone Selection

D3

D2

D1

D0 Frequency (Hz)

Use

12

0000

1100

1700

Key Pulse (KP)

0

0

0

1

700

900

Digit 1

0010

700

1100

Digit 2

0011

900

1100

Digit 3

0100

700

1300

Digit 4

0101

900

1300

Digit 5

0110

1100

1300

Digit 6

0111

700

1500

Digit 7

1000

900

1500

Digit 8

1001

1100

1500

Digit 9

1010

1300

1500

Digit 0

1011

1500

1700

ST

1100

900

1700

ST1

1101

1300

1700

ST2

1110

700

1700

ST3

Pin Function

Pin

Function

CE

Latches data and enables output (active low

input).

D0 - D3

Data input pins. (See Data/Tone Selection.)

D4-D5

Leave open.

MUTE

Output indicates that a signal is being

generated at OUTDRIVE.

OUTDRIVE

Linear buffered tone output.

V

DD

Most positive power supply input pin.

V

REF

Internally generated mid-power supply

voltage (output).

V

SS

Most negative power supply input pin.

X

IN

Crystal oscillator or digital clock input.

X

OUT

Crystal oscillator output.

M-993

www.clare.com

3

Rev. 1

A typical control sequence for the M-993 is: (1) set

data lines Selection for data settings for a particular

tone pair output).to desired frequency selection, (2)

wait for data lines to settle, (3) drive the chip enable

(CE) low, (4) maintain CE low for desired tone duration

(Note: data lines may be changed after data hold

time), and (5) return CE to a logic high.

In a bus-oriented system, noise on the data lines may

propagate through the device and appear at the out-

put. To safeguard against this, use an external latch to

clock the data into the device. In addition, it is good

practice to bypass the V

capacitor (~0.01mF) to reduce power supply noise.

The designer should be aware of device timing

requirements and design accordingly. Beware of hard-

wiring the data input pins for dedicated tone genera-

tion. An RC network like that shown in Power-On

Reset Circuit should be used to momentarily reset the

device immediately following a power-up to ensure

reliable operation.

Power-On Reset Circuit