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ISL29028IROZ 데이터시트(PDF) 4 Page - Intersil Corporation

부품명 ISL29028IROZ
상세설명  Low Power Ambient Light and Proximity Sensor with Intelligent Interrupt and Sleep Modes
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제조업체  INTERSIL [Intersil Corporation]
홈페이지  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL29028IROZ 데이터시트(HTML) 4 Page - Intersil Corporation

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4
FN6780.2
November 4, 2011
IIRDR_LEAK IRDR Leakage Current
PROX_EN = 0; VDD = 3.63V (Note 8)
0.001
1
µA
VIRDR
Acceptable Voltage Range on IRDR Pin
Register bit PROX_DR = 0
0.5
4.3
V
tPULSE
Net IIRDR On Time Per PROX Reading
100
µs
VREF
Voltage of REXT Pin
0.51
V
FI2C
I2C Clock Rate Range
400
kHz
VI2C
Supply Voltage Range for I2C Interface
1.7
3.63
V
VIL
SCL and SDA Input Low Voltage
0.55
V
VIH
SCL and SDA Input High Voltage
1.25
V
ISDA
SDA Current Sinking Capability
VOL = 0.4V
3
5
mA
IINT
INT Current Sinking Capability
VOL = 0.4V
3
5
mA
PSRRIRDR (ΔIIRDR)/(ΔVIRDR)
PROX_DR = 0; VIRDR = 0.5V to 4.3V
4
mA/V
NOTES:
6. An LED is used in production test. The LED irradiance is calibrated to produce the same DATA count against a fluorescent light
source of the same lux level.
7. An 850nm infrared LED is used to test PROX/IR sensitivity in an internal test mode.
8. Ability to guarantee IIRDR leakage of ~1nA is limited by test hardware.
9. For ALS applications under light-distorting glass, please see the section titled ALS Range 1 Considerations.
Electrical Specifications VDD = 3.0V, TA = +25°C, REXT = 499kΩ 1% tolerance. (Continued)
PARAMETER
DESCRIPTION
CONDITION
MIN TYP MAX UNIT
I2C Electrical Specifications For SCL and SDA unless otherwise noted, VDD = 3V, TA = +25°C, REXT = 499kΩ 1%
tolerance (Note 10).
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP MAX UNIT
VI2C
Supply Voltage Range for I2C Interface
1.7
3.63
V
fSCL
SCL Clock Frequency
400
kHz
VIL
SCL and SDA Input Low Voltage
0.55
V
VIH
SCL and SDA Input High Voltage
1.25
V
Vhys
Hysteresis of Schmitt Trigger Input
0.05VDD
V
VOL
Low-level output voltage (open-drain) at
4mA sink current
0.4
V
Ii
Input Leakage for each SDA, SCL pin
-10
10
µA
tSP
Pulse Width of Spikes that must be
Suppressed by the Input Filter
50
ns
tAA
SCL Falling Edge to SDA Output Data Valid
900
ns
Ci
Capacitance for each SDA and SCL pin
10
pF
tHD:STA
Hold Time (Repeated) START Condition
After this period, the first clock pulse
is generated
600
ns
tLOW
LOW Period of the SCL clock
Measured at the 30% of VDD
crossing
1300
ns
tHIGH
HIGH period of the SCL Clock
600
ns
tSU:STA
Set-up Time for a Repeated START
Condition
600
ns
tHD:DAT
Data Hold Time
30
ns
tSU:DAT
Data Set-up Time
100
ns
tR
Rise Time of both SDA and SCL Signals
(Note 11)
20 + 0.1xCb
ns
ISL29028


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