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MC-4R512FKE8D-653 데이터시트(PDF) 9 Page - Elpida Memory

부품명 MC-4R512FKE8D-653
상세설명  Direct Rambus DRAM RIMM Module 512M-BYTE (256M-WORD x 18-BIT)
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제조업체  ELPIDA [Elpida Memory]
홈페이지  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

MC-4R512FKE8D-653 데이터시트(HTML) 9 Page - Elpida Memory

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Data Sheet
E0076N20 (Ver 2.0)
9
MC-4R512FKE8D
AC Electrical Specifications
Symbol
Parameter and Conditions
MIN.
TYP.
MAX.
Unit
Z
Module Impedance of RSL signals
25.2
28.0
30.8
Module Impedance of SCK and CMD signals
23.8
28.0
32.2
TPD
Average clock delay from finger to finger of all RSL clock nets
2.11
ns
(CTM, CTMN,CFM, and CFMN)
∆TPD
Propagation delay variation of RSL signals with respect to TPD
Note1,2
−24
+24
ps
∆TPD-CMOS
Propagation delay variation of SCK signal with respect to an average clock
delay
Note1
−250
+250
ps
∆TPD- SCK,CMD Propagation delay variation of CMD signal with respect to SCK signal
−200
+200
ps
Vα/VIN
Attenuation Limit
-845
25.0
%
-745
25.0
-653
18.5
VXF/VIN
Forward crosstalk coefficient
-845
8.0
%
(300ps input rise time 20% - 80%)
-745
8.0
-653
8.0
VXB/VIN
Backward crosstalk coefficient
-845
2.5
%
(300ps input rise time 20% - 80%)
-745
2.5
-653
2.5
RDC
DC Resistance Limit
-845
1.2
-745
1.2
-653
1.2
Notes 1. TPD or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM,
CTMN, CFM, and CFMN).
2. If the RIMM module meets the following specification, then it is compliant to the specification.
If the RIMM module does not meet these specifications, then the specification can be adjusted by the
“Adjusted
∆TPD Specification” table.
Adjusted
∆∆∆∆TPD Specification
Symbol
Parameter and conditions
Adjusted MIN./MAX.
Absolute
Unit
MIN.
MAX.
∆TPD
Propagation delay variation of RSL signals with respect to TPD
+/
− [24+(18*N*∆Z0)] Note
−50
50
ps
Note N = Number of RDRAM devices installed on the RIMM module.
∆Z0 = delta Z0% = (MAX. Z0 MIN. Z0) / (MIN. Z0)
(MAX. Z0 and MIN. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers
on the module.)


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