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L6386ADTR 데이터시트(PDF) 7 Page - STMicroelectronics |
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L6386ADTR 데이터시트(HTML) 7 Page - STMicroelectronics |
7 / 15 page DocID14914 Rev 2 7/15 L6386AD Electrical characteristics 15 3.3 Timing diagram Figure 3. Input/output timing diagram Symbol Pin Parameter Test condition Min Typ Max Unit Logic inputs Vil 1, 2, 3 Low level logic voltage 1.5 V Vih High level logic voltage 3.6 V Iih High level logic input current VIN = 15 V 50 70 A Iil Low level logic input current VIN = 0 V 1 A Sense comparator Vio Input offset voltage -10 10 mV Iio 6 Input bias current Vcin 0.5 0.2 A Vol 2 Open drain low level output voltage Iod = -2.5 mA 0.8 V Vref Comparator reference voltage 0.46 0.50 0.54 V 1. RDS(on) is tested in the following way: where I1 is the pin 14 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2. Table 7. DC operation electrical characteristics (continued) (VCC = 15 V; TJ = 25 °C) RDSON VCC VCBOOT1 – VCC VCBOOT2 – – I1 VCC,VCBOOT1 I 2 VCC,VCBOOT2 – ------------------------------------------------------------------------------------------------------- = HIN LIN SD HOUT LOUT VREF VCIN DIAG Note: SD active condition is latched until next negative IN edge. D97IN522A |
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