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전자부품 데이터시트 검색엔진 |
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AM1707 데이터시트(PDF) 1 Page - Texas Instruments |
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AM1707 데이터시트(HTML) 1 Page - Texas Instruments |
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1 / 201 page  Product Folder Sample & Buy Technical Documents Tools & Software Support & Community AM1707 www.ti.com SPRS637E – FEBRUARY 2010 – REVISED JUNE 2014 AM1707 ARM® Microprocessor 1 AM1707 ARM Microprocessor 1.1 Features 1 • Clock Gating • 375- and 456-MHz ARM926EJ-S™ RISC Core • Entire Subsystem Under a Single PSC Clock – 32-Bit and 16-Bit (Thumb®) Instructions Gating Domain – Single-Cycle MAC – Dedicated Interrupt Controller – ARM Jazelle® Technology – Dedicated Switched Central Resource – Embedded ICE-RT™ for Real-Time Debug • Multimedia Card (MMC)/Secure Digital (SD) Card • ARM9™ Memory Architecture Interface with Secure Data I/O (SDIO) – 16KB of Instruction Cache • Two Master and Slave Inter-Integrated Circuit (I2C – 16KB of Data Cache Bus™) – 8KB of RAM (Vector Table) • One Host-Port Interface (HPI) with 16-Bit-Wide – 64KB of ROM Muxed Address/Data Bus for High Bandwidth • Enhanced Direct Memory Access Controller 3 • USB 1.1 OHCI (Host) with Integrated PHY (USB1) (EDMA3): • USB 2.0 OTG Port with Integrated PHY (USB0) – 2 Transfer Controllers – USB 2.0 High- and Full-Speed Client – 32 Independent DMA Channels – USB 2.0 High-, Full-, and Low-Speed Host – 8 Quick DMA Channels – End Point 0 (Control) – Programmable Transfer Burst Size – End Points 1,2,3,4 (Control, Bulk, Interrupt or • 128KB of RAM Memory ISOC) RX and TX • 3.3-V LVCMOS I/Os (Except for USB Interfaces) • Three Multichannel Audio Serial Ports (McASPs): • Two External Memory Interfaces: – Six Clock Zones and 28 Serial Data Pins – EMIFA – Supports TDM, I2S, and Similar Formats • NOR (8- or 16-Bit-Wide Data) – DIT-Capable (McASP2) • NAND (8- or 16-Bit-Wide Data) – FIFO Buffers for Transmit and Receive • 16-Bit SDRAM with 128-MB Address Space • 10/100 Mbps Ethernet MAC (EMAC): – EMIFB – IEEE 802.3 Compliant (3.3-V I/O Only) • 32-Bit or 16-Bit SDRAM with 256-MB – RMII Media-Independent Interface Address Space – Management Data I/O (MDIO) Module • Three Configurable 16550-Type UART Modules: • Real-Time Clock (RTC) with 32-kHz Oscillator and – UART0 with Modem Control Signals Separate Power Rail – 16-Byte FIFO • One 64-Bit General-Purpose Timer (Configurable – 16x or 13x Oversampling Option as Two 32-Bit Timers) – Autoflow Control Signals (CTS, RTS) on UART0 • One 64-Bit General-Purpose Watchdog Timer Only (Configurable as Two 32-Bit General-Purpose • LCD Controller Timers) • Two Serial Peripheral Interfaces (SPIs) Each with • Three Enhanced Pulse Width Modulators One Chip Select (eHRPWMs): • Programmable Real-Time Unit Subsystem – Dedicated 16-Bit Time-Base Counter with (PRUSS) Period and Frequency Control – Two Independent Programmable Real-Time Unit – 6 Single Edge, 6 Dual Edge Symmetric, or 3 (PRU) Cores Dual Edge Asymmetric Outputs • 32-Bit Load-Store RISC Architecture – Dead-Band Generation • 4KB of Instruction RAM per Core – PWM Chopping by High-Frequency Carrier • 512 Bytes of Data RAM per Core – Trip Zone Input • PRUSS can be Disabled via Software to • Three 32-Bit Enhanced Capture (eCAP) Modules: Save Power – Configurable as 3 Capture Inputs or 3 Auxiliary – Standard Power-Management Mechanism Pulse Width Modulator (APWM) Outputs 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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