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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DAC3484 데이터시트(PDF) 8 Page - Texas Instruments |
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DAC3484 데이터시트(HTML) 8 Page - Texas Instruments |
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8 / 90 page  DAC3484 SLAS749C – MARCH 2011 – REVISED AUGUST 2012 www.ti.com PIN FUNCTIONS (continued) PIN I/O DESCRIPTION NAME NO. A10, A13, A14, B10, B11, B12, B13, C5, C6, C7, C8, C9, C10, C13, D8, D13, D14, E8, E12, E13, F6, F7, F8, F9, F12, F13, G6, G7, G8, GND G9, G13, I These pins are ground for all supplies. G14, H6, H7, H8, H9, H13, H14, J6, J7, J8, J9, J12, J13, K8, K13, L8, L13, L14, M5, M6, M7, M8, M9, M10, M11, M12, M13, N13, P13, P14 IOUTAP B14 O A-Channel DAC current output. IOUTAN C14 O A-Channel DAC complementary current output. IOUTBP F14 O B-Channel DAC current output. IOUTBN E14 O B-Channel DAC complementary current output. IOUTCP J14 O C-Channel DAC current output. IOUTCN K14 O C-Channel DAC complementary current output. IOUTDP N14 O D-Channel DAC current output. IOUTDN M14 O D-Channel DAC complementary current output. D5, D6, G5, IOVDD I Supply voltage for all digital I/O. (3.3 V) H5, L5, L6 LPF D12 I PLL loop filter connection. If not using the clock multiplying PLL, the LPF pin can be left unconnected. LVPECL output strobe positive input. This positive/negative pair is captured with the rising edge of OSTRP A9 I DACCLKP/N. It is used for multiple DAC synchronization. If unused it can be left unconnected. OSTRN B9 I LVPECL output strobe negative input. (See the OSTRP description) Optional LVDS positive input parity bit. The PARITYP/N LVDS pair has an internal 100 Ω termination PARITYP N5 I resistor. If unused it can be left unconnected. PARITYN P5 I Optional LVDS negative input parity bit. PLLAVDD C11, D11 I PLL analog supply voltage. (3.3 V) SCLK P9 I Serial interface clock. Internal pull-down. SDENB P10 I Active low serial data enable, always an input to the DAC3484. Internal pull-up. SDIO P11 I/O Serial interface data. Bi-directional in 3-pin mode (default) and 4-pin mode. Internal pull-down. Uni-directional serial interface data in 4-pin mode. The SDO pin is three-stated in 3-pin interface SDO P12 O mode (default). SLEEP B8 I Active high asynchronous hardware power-down input. Internal pull-down. Optional LVDS SYNC positive input. The SYNCP/N LVDS pair has an internal 100 Ω termination SYNCP A5 I resistor. If unused it can be left unconnected. SYNCN B5 I LVDS SYNC negative input. Active low input for chip RESET, which resets all the programming registers to their default state. RESETB N10 I Internal pull-up. 8 Copyright © 2011–2012, Texas Instruments Incorporated |
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