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TSB43AB22PDT 데이터시트(PDF) 2 Page - Texas Instruments

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부품명 TSB43AB22PDT
상세설명  Integrated 1394a-2000 OHCI PHY/Link-Layer Controller
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
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DESCRIPTION
Not Recommended for New Designs
TSB43AB22
SLLA208 – JUNE 2006
The Texas Instruments TSB43AB22 device is an integrated 1394a-2000 OHCI PHY/link-layer controller (LLC)
device that is fully compliant with the PCI Local Bus Specification, the PCI Bus Power Management Interface
Specification, IEEE Std 1394-1995, IEEE Std 1394a-2000, and the 1394 Open Host Controller Interface
Specification. It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus at 100M bits/s,
200M bits/s, and 400M bits/s. The TSB43AB22 device provides two 1394 ports that have separate cable bias
(TPBIAS). The TSB43AB22 device also supports the IEEE Std 1394a-2000 power-down features for
battery-operated applications and arbitration enhancements.
As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal
control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through
configuration cycles specified by PCI, and it provides plug-and-play (PnP) compatibility. Furthermore, the
TSB43AB22 device is compliant with the PCI Bus Power Management Interface Specification as specified by the
PC 2001 Design Guide requirements. The TSB43AB22 device supports the D0, D1, D2, and D3 power states.
The TSB43AB22 design provides PCI bus master bursting, and it is capable of transferring a cacheline of data
at 132M bytes/s after connection to the memory controller. Because PCI latency can be large, deep FIFOs are
provided to buffer the 1394 data.
The TSB43AB22 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2
performance. The TSB43AB22 device also provides multiple isochronous contexts, multiple cacheline burst
transfers, advanced internal arbitration, and bus-holding buffers.
An advanced CMOS process achieves low power consumption and allows the TSB43AB22 device to operate at
PCI clock rates up to 33 MHz.
The TSB43AB22 PHY-layer provides the digital and analog transceiver functions needed to implement a
two-port node in a cable-based 1394 network. Each cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission.
The TSB43AB22 PHY-layer requires only an external 24.576-MHz crystal as a reference for the cable ports. An
external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop
(PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to
provide the clock signals that control transmission of the outbound encoded strobe and data information. A
49.152-MHz clock signal is supplied to the integrated LLC for synchronization and is used for resynchronization
of the received data.
Data bits to be transmitted through the cable ports are received from the integrated LLC and are latched
internally in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and
transmitted at 98.304M, 196.608M, or 393.216M bits/s (referred to as S100, S200, or S400 speeds, respectively)
as the outbound data-strobe information stream. During transmission, the encoded data information is
transmitted differentially on the twisted-pair B (TPB) cable pair(s), and the encoded strobe information is
transmitted differentially on the twisted-pair A (TPA) cable pair(s).
During packet reception, the TPA and TPB transmitters of the receiving cable port are disabled, and the
receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the
encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded
to recover the receive clock signal and the serial data bits. The serial data bits are resynchronized to the local
49.152-MHz system clock and sent to the integrated LLC. The received data is also transmitted (repeated) on
the other active (connected) cable ports.
Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during
initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the
arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this
common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition,
the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the
remotely supplied twisted-pair bias voltage.
The TSB43AB22 device provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The
PHY layer contains two independent TPBIAS circuits. This bias voltage, when seen through a cable by a remote
receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an
external filter capacitor of 1.0 µF.
2
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