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TSB12LV32PZG4 데이터시트(PDF) 2 Page - Texas Instruments

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부품명 TSB12LV32PZG4
상세설명  IEEE 1394-1995 and P1394a Compliant General-Purpose Link-Layer Controller for Computer Peripherals and Consumer Audio/Video Electronics
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TSB12LV32
TSB12LV32I
SLLA215 – JUNE 2006
The data-mover block in GP2Lynx handles the external memory interface of large data blocks. This local bus
interface can be configured either to transmit or receive data packets. The packets can be either asynchronous,
isochronous, or asynchronous streaming data packets. The data-mover (DM) port can receive any type of
packet, but it can only transmit one type of packet at a time: isochronous data packets, asynchronous data
packets, or asynchronous stream data packets.
The internal FIFO is separated into an asynchronous transmit FIFO (ATF) and a general receive FIFO (GRF),
each of 520 quadlets (2 Kbytes). Asynchronous and/or isochronous receive packets can be routed to either the
DM port or the GRF via the receiver routing control logic. Asynchronous data packets or asynchronous stream
data packets can be transmitted from the DM port or the internal FIFO: ATF. If there is contention the ATF has
priority and is transmitted first. Isochronous packets can only be transmitted by the data-mover port.
The LLC also provides the capability to receive status information from the physical layer device and to access
the physical layer control and status registers by the application software.
NOTE:
This product is for high-volume applications only. For a complere datasheet or more
information contact support@ti.com.
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