전자부품 데이터시트 검색엔진 |
|
ADC108S102CIMT 데이터시트(PDF) 6 Page - Texas Instruments |
|
ADC108S102CIMT 데이터시트(HTML) 6 Page - Texas Instruments |
6 / 28 page ADC108S102 SNAS336B – SEPTEMBER 2005 – REVISED MARCH 2013 www.ti.com ADC108S102 Timing Specifications The following specifications apply for VA = VD = +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 8 MHz to 16 MHz, fSAMPLE = 500 kSPS to 1 MSPS, and CL = 50pF. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Limits Symbol Parameter Conditions Typical Units (1) tCSH CS Hold Time after SCLK Rising Edge 0 10 ns (min) CS Setup Time prior to SCLK Rising tCSS 5 10 ns (min) Edge tEN CS Falling Edge to DOUT enabled 5 30 ns (max) DOUT Access Time after SCLK Falling tDACC 17 27 ns (max) Edge DOUT Hold Time after SCLK Falling tDHLD 4 ns (typ) Edge DIN Setup Time prior to SCLK Rising tDS 3 10 ns (min) Edge tDH DIN Hold Time after SCLK Rising Edge 3 10 ns (min) tCH SCLK High Time 0.4 x tSCLK ns (min) tCL SCLK Low Time 0.4 x tSCLK ns (min) DOUT falling 2.4 20 ns (max) CS Rising Edge to DOUT High- tDIS Impedance DOUT rising 0.9 20 ns (max) (1) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level). 6 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: ADC108S102 |
유사한 부품 번호 - ADC108S102CIMT |
|
유사한 설명 - ADC108S102CIMT |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |