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ADC10D040 데이터시트(PDF) 9 Page - Texas Instruments |
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ADC10D040 데이터시트(HTML) 9 Page - Texas Instruments |
9 / 32 page ADC10D040 www.ti.com SNAS149G – OCT 2001 – REVISED MARCH 2013 AC Electrical Characteristics OS = Low (Multiplexed Mode) (continued) The following specifications apply for VA = VD = +3.3 VDC, VDR = +2.5VDC, VREF = 1.4 VDC, GAIN = OF = 0V, OS = 0V, VIN (a.c. coupled) = FSR = 1.4 VP-P, CL = 15 pF, fCLK = 40 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C (1) Units Symbol Parameter Conditions Typical(2) Limits(3) (Limits) tWUPD PD Low to 1/2 LSB Accurate Conversion (Wake-Up Time) <1 ms tWUSB STBY Low to 1/2 LSB Accurate Conversion (Wake-Up Time) 800 ns AC Electrical Characteristics OS = High (Parallel Mode) The following specifications apply for VA = VD = +3.3 VDC, VDR = +2.5VDC, VREF = 1.4 VDC, GAIN = OF = 0V, OS = +3.3V, VIN (a.c. coupled) = FSR = 1.0 VP-P, CL = 15 pF, fCLK = 40 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C (1) Units Symbol Parameter Conditions Typical(2) Limits(3) (Limits) fCLK1 Maximum Clock Frequency 45 40 MHz (min) fCLK2 Minimum Clock Frequency 20 MHz 45 % (min) Duty Cycle 50 55 % (max) Pipeline Delay (Latency) 2.5 Clock Cycles tr, tf Output Rise and Fall Times 9 ns tOC OC Pulse Width 10 ns Output Delay from CLK Edge to Data tOD 16 22 ns (max) Valid tDIQ I/Q Output Delay 13 ns tAD Sampling (Aperture) Delay 2.2 ns tAJ Aperture Jitter <10 ps (rms) tVALID Data Valid Time 16 ns Overrange Recovery Time Differential VIN step from 1.5V to 0V 50 ns PD Low to 1/2 LSB Accurate Conversion tWUPD < 1 ms (Wake-Up Time) STBY Low to 1/2 LSB Accurate tWUSB 800 ns Conversion (Wake-Up Time) (1) The inputs are protected as shown below. Input voltage magnitude up to 300 mV beyond the supply rails will not damage this device. However, errors in the A/D conversion can occur if the input goes beyond the limits given in these tables. (2) Typical figures are at TJ = 25°C, and represent most likely parametric norms. (3) Test limits are specified to TI's AOQL (Average Outgoing Quality Level). Performance is specified only at VREF = 1.4V and a clock duty cycle of 50%. The limits for VREF and clock duty cycle specify the range over which reasonable performance is expected. Tests are performed and limits specified with clock low and high levels of 0.3V and VD−0.3V, respectively. Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: ADC10D040 |
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유사한 설명 - ADC10D040_14 |
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