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ADC0848CCVX 데이터시트(PDF) 4 Page - Texas Instruments

부품명 ADC0848CCVX
상세설명  ADC0844/ADC0848 8-Bit 關P Compatible A/D Converters with Multiplexer Options
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홈페이지  http://www.ti.com
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ADC0844, ADC0848
SNAS523D – JUNE 1999 – REVISED MARCH 2013
www.ti.com
Electrical Characteristics (continued)
The following specifications apply for VCC = 5 VDC unless otherwise specified. Boldface limits apply from TMIN to TMAX; all
other limits TA = Tj = 25°C.
ADC0844CCN,
ADC0848BCN,
ADC0844BCJ(1)
ADC0848CCN,
ADC0844CCJ(1)
Limit
ADC0848BCV,
Parameter
Conditions
Units
ADC0848CCV
Tested
Design
Tested
Design
Typ(2)
Typ(2)
Limit(3)
Limit(4)
Limit(3)
Limit(4)
VCC = 4.75V, IOUT = −360 μA
2.4
2.8
2.4
V
VOUT(1), Logical “1” Output Voltage (Min)
IOUT = −10 μA
4.5
4.6
4.5
V
VOUT(0), Logical “0” Output Voltage (Max) VCC = 4.75V, IOUT = 1.6 mA
0.4
0.34
0.4
V
VOUT = 0V
−0.01
−3
−0.01
−0.3
−3
μA
IOUT, TRI-STATE Output Current (Max)
VOUT = 5V
0.01
3
0.01
0.3
3
μA
ISOURCE, Output Source Current (Min)
VOUT = 0V
−14
−6.5
−14
−7.5
−6.5
mA
ISINK, Output Sink Current (Min)
VOUT = VCC
16
8.0
16
9.0
8.0
mA
ICC, Supply Current (Max)
CS = 1, VREF Open
1
2.5
1
2.3
2.5
mA
AC Electrical Characteristics
The following specifications apply for VCC = 5VDC, tr = tf = 10 ns unless otherwise specified. Boldface limits apply from TMIN
to TMAX; all other limits TA = Tj = 25°C.
Tested
Design
Parameter
Conditions
Typ(1)
Units
Limit(2)
Limit(3)
tC, Maximum Conversion Time (See Figure 7)
30
40
60
μs
tW(WR), Minimum WR Pulse Width
See(4)
50
150
ns
tACC, Maximum Access Time (Delay from Falling Edge of RD to
CL = 100 pF
(4)
145
225
ns
Output Data Valid)
t1H, t0H, TRI-STATE Control (Maximum Delay from Rising Edge of
CL = 10 pF, RL = 10k
(4)
125
200
ns
RD to Hi-Z State)
tWI, tRI, Maximum Delay from Falling Edge of WR or RD to Reset
200
400
ns
of INTR
See(4)
tDS, Minimum Data Set-Up Time
50
100
ns
tDH, Minimum Data Hold Time
0
50
ns
CIN, Capacitance of Logic Inputs
5
pF
COUT, Capacitance of Logic Outputs
5
pF
(1)
Typical figures are at 25°C and represent most likely parametric norm.
(2)
Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
(3)
Design limits are specified by not 100% tested. These limits are not used to calculate outgoing quality levels.
(4)
The temperature coefficient is 0.3%/°C.
4
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