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HDMP-1012 데이터시트(HTML) 6 Page - Agilent(Hewlett-Packard)

부품명 HDMP-1012
상세내용  4Low Cost Gigabit Rate Transmit/Receive Chip Set
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제조사  HP [Agilent(Hewlett-Packard)]
홈페이지  http://www.home.agilent.com
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HDMP-1012 데이터시트(HTML) 6 Page - Agilent(Hewlett-Packard)

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578
the transmitter. The clock
generator section performs the
clock multiplication to the
necessary serial clock rate.
By setting EHCLKSEL high, the
user may provide an external high
speed serial clock at STRBIN.
This clock is used directly by the
high speed serial circuitry to
output the serial data.
Control Logic and C-Field
Encoder
The Control Logic is responsible
for determining what information
is serially sent to the output. If
CAV* is low, it sends the data at
D0..D8 and D9..D17 as control
word information. If CAV* is high
and DAV* is low, it sends parallel
word data at the data inputs. If
neither CAV* nor DAV* is set low,
then the transmitter assumes the
link is not being used. In this
state, the control logic triggers
the Data Encoder to send Fill
Frames to maintain the link DC
balance and allow the receiver to
HDMP-1012 Tx Block
Diagram
The HDMP-1012 was designed to
accept 16 or 20 bit wide parallel
data and transmit it over a high
speed serial line, while minimizing
the user’s necessary interface to
the high speed circuitry. In order
to accomplish this task, the
HDMP-1012 performs the
following functions:
• Parallel Word Input
• High Speed Clock Multiplication
• Frame Encoding
• Parallel to Serial Multiplexing
PLL/Clock Generator
The Phase Lock-loop and Clock
Generator are responsible for
generating all internal clocks
needed by the transmitter to
perform its functions. These
clocks are based on a supplied
frame clock (STRBIN) and control
signals (M20SEL, MDFSEL,
EHCLKSEL, DIV1, DIV0). In
normal operation (MDFSEL=0),
STRBIN is expected to be the
incoming frame clock. The PLL/
Clock Generator locks on to this
incoming rate and multiplies the
clock up to the needed high speed
serial clock. Based on M20SEL,
which determines whether the
incoming data frame is 16 or 20
bits wide, the PLL/Clock
Generator multiplies the frame
rate clock by 20 or 24
respectively (data bits + 4 control
bits). DIV1/DIV0 are set to inform
the transmitter of the frequency
range of the incoming data
frames. The internal frame rate
clock is accessible through
STRBOUT and the high speed
serial clock is accessible through
HCLK.
When MDFSEL is set high, the
transmitter is in Double Frame
Mode. Using this option, the user
may send a 32 or 40 bit wide data
frame in two segments while
supplying the original 32 or 40 bit
frame clock at STRBIN. Doubling
of the frame rate is performed by
Figure 4. HDMP-1012 Transmitter Block Diagram.
ED
CONTROL
LOGIC
+
C-FIELD
ENCODER
FF
CAV*
DAV*
FLAG
D0-D19
RST*
D-FIELD
ENCODER
SIGN
FRAME
MUX
PLL / CLOCK
GENERATOR
OUTPUT
SELECT
CAP0
CAP1
0.1 µF
STRBOUT
HCLK
LOCKED
DOUT
LOUT
LOOPEN
INV
INTERNAL
CLOCKS
INPUT
LATCH


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