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HDMP-1012 데이터시트(HTML) 20 Page - Agilent(Hewlett-Packard)

부품명 HDMP-1012
상세내용  4Low Cost Gigabit Rate Transmit/Receive Chip Set
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제조사  HP [Agilent(Hewlett-Packard)]
홈페이지  http://www.home.agilent.com
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HDMP-1012 데이터시트(HTML) 20 Page - Agilent(Hewlett-Packard)

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592
Rx I/O Definition (cont’d.)
Name
Pin
Type
Signal
ECLGND
32
S
ECL Ground: Normally 0 volts. This ground is used for the ECL pad
52
drivers. For best performance it is suggested that coupling of the noisy
53
ECLGND to the clean GND and HGND grounds be minimized.
72
EQEN
19
I-ECL
Enable Input for Cable Equalization: When asserted, this signal
activates the cable equalization amplifier on the DIN, DIN* serial
data inputs.
ERROR
40
O-ECL
Received Data Error: Asserted when a frame is received that does
not correspond to either a valid Data, Control, or Fill frame encoding.
When FLAGSEL is not active, the Rx chip also tests for strict
alternation of flag bits during data frames. A flag bit alternation
error will also cause an ERROR indication.
FCLK
75
O-ECL
Frame Clock Monitor: Leave unterminated in normal use.
FDIS
20
I-ECL
Frequency Detector Disable Input: When active, this input
disables the Rx PLL Frequency detector and enables a phase detector.
The Frequency detector is used during the start-up sequence to
acquire wide-band lock on Fill Frames, but must be disabled prior to
sending data patterns. This input is normally controlled by the Rx
state machine.
FF
39
O-ECL
Fill Frame Status: During a given STRBOUT clock cycle, if neither
DAV, CAV, or ERROR are active, then the currently received frame
is a Fill frame. The type of fill frame received is indicated by the FF
pin. If FF is low, then FF0 has been received. If FF is high, then
either FF1a or FF1b has been received.
FLAG
45
O-ECL
Flag Bit: If both Tx and Rx have FLAGSEL asserted, this output
indicates the value of the transmitted flag bit, then this received bit
can be treated just like an extra data bit. If both Tx and Rx have
FLAGSEL set to low, FLAG is used to differentiate the even frame
from the odd frame in the line code.
FLAGSEL
34
I-ECL
Flag Bit Mode Select: When this input is high, the extra FLAG bit
output is effectively an extra transparent data bit. Otherwise, the
FLAG bit is checked for alternation during data frames. Any break in
strict alternation results in an ERROR indication to the user.
GND
5
S
Ground: Normally 0 volts. This ground is used for all the core logic
23
other than the output drivers.
24
33
43
44
63
64
73
78
HGND
13
S
High Speed Ground: Normally 0 volts. This ground is used to
provide clean references for the high speed DIN, DIN*, LIN, LIN*,
TCLK, TCLK* inputs.


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