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AD1848K 데이터시트(PDF) 11 Page - Analog Devices |
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AD1848K 데이터시트(HTML) 11 Page - Analog Devices |
11 / 28 page AD1848K REV. 0 –11– CONTROL REGISTERS Control Register Architecture The AD1848K SoundPort Stereo Codec accepts both data and control information through its byte-wide parallel port. Indirect addressing minimizes the number of external pins required to access all 21 of its byte-wide internal registers. Only two external address pins, ADR1:0, are required to accomplish all data and control transfers. These pins select one of five direct registers. (ADR1:0 = 3 addresses two registers, depending on whether the transfer is a playback or a capture.) ADR1:0 Register Name 0 Index Address Register 1 Indexed Data Register 2 Status Register 3 PIO Data Registers Figure 4. AD1848K Direct Register Map A write to or a read from the Indexed Data Register will access the indirect register which is indexed by the value most recently written to the Index Address Register. The Status Register and the PIO Data Register are always accessible directly, without in- dexing. The 16 indirect registers are indexed in Figure 5. Index Register Name 0 Left Input Control 1 Right Input Control 2 Left Aux #1 Input Control 3 Right Aux #1 Input Control 4 Left Aux #2 Input Control 5 Right Aux #2 Input Control 6 Left Output Control 7 Right Output Control 8 Clock and Data Format 9 Interface Configuration 10 Pin Control 11 Test and Initialization 12 Miscellaneous Information 13 Digital Mix 14 Upper Base Count 15 Lower Base Count Figure 5. AD1848K Indirect Register Map A detailed map of all direct and indirect register contents is summarized for reference as follows: Direct Registers: ADR1:0 Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 0 INIT MCE TRD res IXA3 IXA2 IXA1 IXA0 1 IXD7 IXD6 IXD5 IXD4 IXD3 IXD2 IXD1 IXD0 2 CU/L CL/R CRDY SOUR PU/L PL/R PRDY INT 3 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Indirect Registers: IXA3:0 Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 0 LSS1 LSS0 LMGE res LIG3 LIG2 LIG1 LIG0 1 RSS1 RSS0 RMGE res RIG3 RIG2 RIG1 RIG0 2 LMX1 res res LX1A4 LX1A3 LX1A2 LX1A1 LX1A0 3 RMX1 res res RX1A4 RX1A3 RX1A2 RX1A1 RX1A0 4 LMX2 res res LX2A4 LX2A3 LX2A2 LX2A1 LX2A0 5 RMX2 res res RX2A4 RX2A3 RX2A2 RX2A1 RX2A0 6 LDM res LDA5 LDA4 LDA3 LDA2 LDA1 LDA0 7 RDM res RDA5 RDA4 RDA3 RDA2 RDA1 RDA0 8 res FMT L/C S/M CFS2 CFS1 CFS0 CSS 9 CPIO PPIO res res ACAL SDC CEN PEN 1 0 XCTL1 XCTL0 res res res res IEN res 1 1 COR PUR ACI DRS ORR1 ORR0 ORL1 ORL0 1 2 res res res res ID3 ID2 ID1 ID0 1 3 DMA5 DMA4 DMA3 DMA2 DMA1 DMA0 res DME 1 4 UB7 UB6 UB5 UB4 UB3 UB2 UB1 UB0 1 5 LB7 LB6 LB5 LB4 LB3 LB2 LB1 LB0 Figure 6. AD1848K Register Summary Note that the only sticky bit in any of the AD1848K control registers is the interrupt (INT) bit. All other bits change with every sample period. OBSOLETE |
유사한 부품 번호 - AD1848K_15 |
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유사한 설명 - AD1848K_15 |
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