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MC146805E2P 데이터시트(PDF) 3 Page - InnovASIC, Inc

부품명 MC146805E2P
상세설명  Microprocessor Unit
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제조업체  INNOVASIC [InnovASIC, Inc]
홈페이지  http://www.innovasic.com
Logo INNOVASIC - InnovASIC, Inc

MC146805E2P 데이터시트(HTML) 3 Page - InnovASIC, Inc

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IA6805E2
Data Sheet
Microprocessor Unit
As of Production Version 00
Copyright
© 2002
ENG21108140100
www.innovasic.com
innovASIC
Customer Support:
The End of Obsolescence
Page 3 of 31
1-888-824-4184
Table 1
I/O Signal Description
The table below describes the I/O characteristics for each signal on the IC. The signal names
correspond to the signal names on the pinout diagrams provided.
SIGNAL NAME
I/O
DESCRIPTION
V DD and V SS
(Power and Ground)
N/A
Source: These two pins provide power to the chip. V DD provides +5 volts (±0.5) power
and V SS is ground.
RESET_n
(Reset)
I
TTL: Input pin that can be used to reset the MPU's internal state by pulling the reset_n
pin low.
IRQ_n
(Interrupt Request)
I
TTL: Input pin that is level and edge sensitive. Can be used to request an interrupt
sequence.
LI
(Load Instruction)
O
TTL with slew rate control: Output pin used to indicate that a next opcode fetch is in
progress. Used only for certain debugging and test systems. Not connected in normal
operation. Overlaps Data Strobe (DS) signal. This output is capable of driving one
standard TTL load and 50pF.
DS
(Data Strobe)
O
TTL with slew rate control: Output pin used to transfer data to or from a peripheral or
memory. DS occurs anytime the MPU does a data read or write and during data transfer
to or from internal memory. DS is available at f OSC ÷ 5 when the MPU is not in the WAIT
or STOP mode. This output is capable of driving one standard TTL load and 130pF.
RW_n
(Read/Write)
O
TTL with slew rate control: Output pin used to indicate the direction of data transfer
from internal memory, I/O registers, and external peripheral devices and memories.
Indicates to a selected peripheral whether the MPU is to read (RW_n high) or write
(RW_n low) data on the next data strobe. This output is capable of driving one standard
TTL load and 130pF.
AS
(Address Strobe)
O
TTL with slew rate control: Output strobe used to indicate the presence of an address
on the 8-bit multiplexed bus. The AS line is used to demultiplex the eight least significant
address bits from the data bus. AS is available at f OSC ÷ 5 when the MPU is not in the
WAIT or STOP modes. This output is capable of driving one standard TTL load and
130pF.
PA0-PA7/PB0-PB7
(Input/Output Lines)
I/O
TTL with slew rate control: These 16 lines constitute Input/Output ports A and B.
Each line is individually programmed to be either an input or output under software
control of the Data Direction Register (DDR) as shown below in Table 1 and Figure 2 .
The port I/O is programmed by writing the corresponding bit in the DDR to a "1" for
output and a "0" for input. In the output mode the bits are latched and appear on the
corresponding output pins. All the DDR's are initialized to a "0" on reset. The output
port registers are not initialized on reset. Each output is capable of driving one standard
TTL load and 50pF.
A8-A12
(High Order Address Lines)
O
TTL with slew rate control:
These five outputs constitute the higher order non-
multiplexed address lines. Each output is capable of driving one standard TTL load and
130pF.
B0-B7
(Address/Data Bus)
I/O
TTL with slew rate control:
These bi-directional lines constitute the lower order
addresses and data. These lines are multiplexed with address present at address strobe
time and data present at data strobe time. When in the data mode, these lines are bi-
directional, transferring data to and from memory and peripheral devices as indicated by
the RW_n pin. As outputs, these lines are capable of driving one standard TTL load and
130pF.
Timer
I
TTL: Input used to control the internal timer/counter circuitry.
OSC1, OSC2
(System Clock)
TTL Oscillator input/output: These pins provide control input for the on-chip clock
oscillator circuits. Either a crystal or external clock is connected to these pins to provide
a system
clock.
The crystal connection is shown in Figure 3 . The OSC1 to bus
transitions for system designs using oscillators slower than 5MHz is shown in Figure 4 .
Crystal
The circuit shown in Figure 3 is recommended when using a crystal. An external CMOS
oscillator is recommended when using crystals outside the specified ranges. To minimize
output distortion and start-up stabilization time, the crystal and components should be
mounted as close to the input pins as possible.
External Clock
When an external clock is used, it should be applied to the OSC1 input with the OSC2
input not connected, as shown in Figure 3 .
I/O


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