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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AD1891 데이터시트(PDF) 2 Page - Analog Devices |
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AD1891 데이터시트(HTML) 2 Page - Analog Devices |
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2 / 20 page  AD1890/AD1891–SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltage +5.0 V Ambient Temperature 25 °C MCLK 20 MHz Load Capacitance 100 pF All minimums and maximums tested except as noted. PERFORMANCE (Guaranteed over 0 °C ≤ T A ≤ 70°C, VDD = 5.0 V ± 10%, 8 MHz ≤ MCLK ≤ 20 MHz) Min Max Units AD1890 Dynamic Range (20 Hz to 20 kHz, –60 dB Input)† 120 dB AD1891 Dynamic Range (20 Hz to 20 kHz, –60 dB Input)† 96 dB Total Harmonic Distortion + Noise† dB AD1890 and AD1891 (20 Hz to 20 kHz, Full-Scale Input, FSOUT/FSIN Between 0.5 and 2.0) –94 dB AD1890 (1 kHz Full-Scale Input, FSOUT/FSIN Between 0.7 and 1.4) –106 dB AD1890 (10 kHz Full-Scale Input, FSOUT/FSIN Between 0.7 and 1.4) –100 dB AD1891 (1 kHz Full-Scale Input, FSOUT/FSIN Between 0.7 and 1.4) –96 dB AD1891 (10 kHz Full-Scale Input, FSOUT/FSIN Between 0.7 and 1.4) –95 dB Interchannel Phase Deviation† 0 Degrees Input and Output Sample Clock Jitter† 10 ns (For ≤ 1 dB Degradation in THD+N with 10 kHz Full-Scale Input, Slow-Settling Mode) DIGITAL INPUTS (Guaranteed over 0 °C ≤ T A ≤ 70°C, VDD = 5.0 V ± 10%, 8 MHz ≤ MCLK ≤ 20 MHz) Min Max Units VIH 2.2 V VIL 0. 8 V IIH @ VIH = +5 V 4 µA IIL @ VIL = 0 V 4 µA VOH @ IOH = –4 mA 3.6 V VOL @ IOL = 4 mA 0.4 V Input Capacitance† 15 pF DIGITAL TIMING (Guaranteed over 0 °C ≤ T A ≤ 70°C, VDD = 5.0 V ± 10%, 8 MHz ≤ MCLK ≤ 20 MHz) Min Max Units tMCLK MCLK Period 50 125 ns fMCLK MCLK Frequency (1/tMCLK) 8 20 MHz tMPWL MCLK LO Pulse Width 20 ns tMPWH MCLK HI Pulse Width 20 ns fLRI LR_I Frequency with 20 MHz MCLK† 10 70 kHz tRPWL RESET LO Pulse Width 100 ns tRS RESET Setup to MCLK Falling 15 ns tBCLK BCLK_I/O Period† 80 ns fBCLK BCLK_I/O Frequency (l/tBCLK)† 12.5 MHz tBPWL BCLK_I/O LO Pulse Width 40 ns tBPWH BCLK_I/O HI Pulse Width 40 ns tWSI WCLK_I Setup to BCLK_I 15 ns tWSO WCLK_O Setup to BCLK_O 30 ns tLRSI LR_I Setup to BCLK_I 15 ns tLRSO LR_O Setup to BCLK_O 30 ns tDS Data Setup to BCLK_I 0 ns tDH Data Hold from BCLK_I 25 ns tDPD Data Propagation Delay from BCLK_O 40 ns tDOH Data Output Hold from BCLK_O 5 ns REV. 0 –2– |
유사한 부품 번호 - AD1891_15 |
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유사한 설명 - AD1891_15 |
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