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GT28F160S3-100 데이터시트(PDF) 10 Page - Intel Corporation

부품명 GT28F160S3-100
상세설명  WORD-WIDE FlashFile MEMORY FAMILY
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제조업체  INTEL [Intel Corporation]
홈페이지  http://www.intel.com
Logo INTEL - Intel Corporation

GT28F160S3-100 데이터시트(HTML) 10 Page - Intel Corporation

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28F160S3, 28F320S3
E
10
ADVANCE INFORMATION
GND
A10
VPP
CE0
A14
VCC
A4
A7
A9
A11
A12
A15
A17
A19
A5
A6
A8
RP#
A13
A16
A21
A20
A2
A1
A3
A18
CE1
NC
NC
NC
BYTE#
DQ7
WP#
WE#
A0
DQ8
DQ1
DQ3
DQ12
DQ6
DQ15
OE#
DQ0
DQ9
DQ2
DQ11
DQ4
DQ13
DQ14
STS
VCC
DQ10
GND
VCC
DQ5
GND
GND A10
VPP CE0 A14
VCC
A4
A7
A9
A11
A12
A15
A17
A19
A5
A6
A8
RP# A13
A16
A21
A20
A2
A1
A3
A18
CE1 NC
NC
NC BYTE#
DQ7 WP# WE#
A0
DQ8 DQ1 DQ3 DQ12 DQ6 DQ15 OE#
DQ0 DQ9 DQ2 DQ11 DQ4 DQ13 DQ14 STS
VCC DQ10 GND VCC DQ5 GND
Bottom View
This is the view of the package as surface mounted on
the board. Note that the signals are mirror imaged.
NOTES:
1.
Figures are not drawn to scale.
2.
Address A21 is not included in the 28F160S3.
3.
More information on µBGA* packages is available by contacting your Intel/Distribution sales office.
Figure 4.
µBGA* Package Pinout
2.0
PRINCIPLES OF OPERATION
The word-wide memories include an on-chip
Write State Machine (WSM) to manage block
erase,
program,
and
lock-bit
configuration
functions. It allows for: 100% TTL-level control
inputs, fixed power supplies during block erasure,
programming, lock-bit configuration, and minimal
processor
overhead
with
RAM-like
interface
timings.
After initial device power-up or return from deep
power-down mode (see Bus Operations), the
device defaults to read array mode. Manipulation
of external memory control pins allow array read,
standby, and output disable operations.
Read Array, Status Register, query, and identifier
codes
can
be
accessed
through
the
CUI
independent
of
the
VPP
voltage.
Proper
programming voltage on VPP enables successful
block
erasure,
program,
and
lock-bit
configuration.
All
functions
associated
with
altering memory contents—block erase, program,
lock-bit configuration—are accessed via the CUI
and verified through the Status Register.


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