AD5045_15 datasheet(5/28 Pages) AD

부품명	AD5045

상세설명	Fully Accurate, 12-/14-/16-Bit, Dual, VOUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP

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5 / 28 page

AD5025/AD5045/AD5065

Rev. 0 | Page 5 of 28

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 3 and

Figure 4. VDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.

Table 4.

Parameter

Symbol

Min

Typ

Max

Unit

SCLK Cycle Time

t11

20

ns

SCLK High Time

t2

10

ns

SCLK Low Time

t3

10

ns

SYNC to SCLK Falling Edge Setup Time

t4

16.5

ns

Data Setup Time

t5

5

ns

Data Hold Time

t6

5

ns

SCLK Falling Edge to SYNC Rising Edge

t7

0

30

ns

Minimum SYNC High Time (Single Channel Update)

t8

2

μs

Minimum SYNC High Time (All Channel Update)

t8

4

μs

SYNC Rising Edge to SCLK Fall Ignore

t9

17

ns

LDAC Pulse Width Low

t10

20

ns

SCLK Falling Edge to LDAC Rising Edge

t11

20

ns

CLR Pulse Width Low

t12

10

ns

SCLK Falling Edge to LDAC Falling Edge

t13

10

ns

CLR Pulse Activation Time

t14

10.6

μs

SCLK Rising Edge to SDO Valid

t152, 3

22

ns

SCLK Falling Edge to SYNC Rising Edge

t162

5

30

ns

SYNC Rising Edge to SCLK Rising Edge

t172

8

ns

SYNC Rising Edge to LDAC/CLR/PDL Falling Edge (Single Channel Update)

t182

2

μs

SYNC Rising Edge to LDAC/CLR/PDL Falling Edge (All Channel Update)

t182

4

μs

PDL Minimum Pulse Width

t19

20

ns

1 Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 5.5 V. Guaranteed by design and characterization; not production tested.

2 Daisy-chain mode only.

3 Measured with the load circuit of Figure 2. t15 determines the maximum SCLK frequency in daisy-chain mode.

Circuit and Timing Diagrams

2mA

IOL

2mA

IOH

VOH (MIN) + VOL (MAX)

2

TO OUTPUT

CL

50pF

Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications

유사한 부품 번호 - AD5045_15

제조업체	부품명	데이터시트	상세설명
Analog Devices	AD5045BRUZ	1Mb / 33P	Fully Accurate 12-/14-/16-Bit VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP Rev. PrB
	AD5045BRUZ	1Mb / 28P	Fully Accurate, 12-/14-/16-Bit, Dual, VOUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP REV. 0
	AD5045BRUZ	1Mb / 25P	Fully Accurate, 12-/14-/16-Bit, Dual, VOUT nanoDAC SPI Interface
	AD5045BRUZ-REEL7	1Mb / 33P	Fully Accurate 12-/14-/16-Bit VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP Rev. PrB
	AD5045BRUZ-REEL7	1Mb / 28P	Fully Accurate, 12-/14-/16-Bit, Dual, VOUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP REV. 0

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유사한 설명 - AD5045_15

제조업체	부품명	데이터시트	상세설명
Analog Devices	AD5025	1Mb / 28P	Fully Accurate, 12-/14-/16-Bit, Dual, VOUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP REV. 0
	AD5025	1Mb / 28P	Fully Accurate, 12-/14-/16-Bit, Dual, VOUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP REV. 0
	AD5065	1Mb / 28P	Fully Accurate, 12-/14-/16-Bit, Dual, VOUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP REV. 0
	AD5064BRUZ-1	2Mb / 28P	Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP Rev. F
	AD5064	2Mb / 28P	Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP Rev. F
	AD5024	2Mb / 28P	Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP Rev. F
	AD5044	2Mb / 28P	Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP Rev. F
	AD5024	1Mb / 28P	Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP REV. 0
	AD5066	617Kb / 24P	Fully Accurate, 16-Bit, Unbuffered VOUT, Quad SPI Interface, 2.7 V to 5.5 V nanoDAC in a TSSOP REV. A
	AD5025	1Mb / 33P	Fully Accurate 12-/14-/16-Bit VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP Rev. PrB

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AD5045 데이터시트(PDF) 5 Page - Analog Devices

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