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GT28F800B3-T120 데이터시트(PDF) 11 Page - Intel Corporation |
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GT28F800B3-T120 데이터시트(HTML) 11 Page - Intel Corporation |
11 / 49 page E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE 11 PRELIMINARY Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions (Continued) Symbol Type Name and Function VCCQ INPUT OUTPUT VCC: Enables all outputs to be driven to 2.0V ±10% while the VCC is at 2.7V. When this mode is used, the VCC should be regulated to 2.7V–2.85V to achieve lowest power operation (see Section 6.1: DC Characteristics: VCCQ = 1.8V–2.2V). This input may be tied directly to VCC (2.7V–3.6V). See the DC Characteristics for further details. VCC DEVICE POWER SUPPLY: 2.7V–3.6V VPP PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or programming data in each block, a voltage of either 2.7V–3.6V or 12V ± 5% must be applied to this pin. When VPP < VPPLK all blocks are locked and protected against Program and Erase commands. Applying 11.4V-12.6V to VPP can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12V for a total of 80 hours maximum (see Section 3.4 for details). GND GROUND: For all internal circuitry. All ground inputs must be connected. NC NO CONNECT: Pin may be driven or left floating. 2.2 Block Organization The Smart 3 Advanced Boot Block is an asymmetrically-blocked architecture that enables system integration of code and data within a single flash device. Each block can be erased independently of the others up to 10,000 times. For the address locations of each block, see the memory maps in Figure 5 (top boot blocking) and Figure 6 (bottom boot blocking). 2.2.1 PARAMETER BLOCKS The Smart 3 Advanced Boot Block flash memory architecture includes parameter blocks to facilitate storage of frequently updated small parameters (e.g., data that would normally be stored in an EEPROM). By using software techniques, the word- rewrite functionality of EEPROMs can be emulated. Each 4-/8-/16-Mbit device contains eight parameter blocks of 4-Kwords (4,096-words) each. 2.2.2 MAIN BLOCKS After the parameter blocks, the remainder of the array is divided into equal size main blocks for data or code storage. Each 16-Mbit device contains thirty-one 32-Kword (32,768-word) blocks. Each 8-Mbit device contains fifteen 32-Kword blocks. Each 4-Mbit device contains seven 32-Kword blocks. |
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