전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

AD5327 데이터시트(PDF) 8 Page - Analog Devices

부품명 AD5327
상세설명  2.5 V to 5.5 V, 400 A, Quad Voltage Output, 8-/10-/12-Bit DACs in 16-Lead TSSOP
Download  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD5327 데이터시트(HTML) 8 Page - Analog Devices

Back Button AD5327_15 Datasheet HTML 4Page - Analog Devices AD5327_15 Datasheet HTML 5Page - Analog Devices AD5327_15 Datasheet HTML 6Page - Analog Devices AD5327_15 Datasheet HTML 7Page - Analog Devices AD5327_15 Datasheet HTML 8Page - Analog Devices AD5327_15 Datasheet HTML 9Page - Analog Devices AD5327_15 Datasheet HTML 10Page - Analog Devices AD5327_15 Datasheet HTML 11Page - Analog Devices AD5327_15 Datasheet HTML 12Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 28 page
background image
AD5307/AD5317/AD5327
Rev. C | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VDD
VOUTA
VOUTB
VOUTC
VREFAB
VREFCD
SDO
SCLK
DIN
GND
VOUTD
DCEN
AD5307/
AD5317/
AD5327
CLR
LDAC
PD
SYNC
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin
No.
Mnemonic
Description
1
CLR
Active Low Control Input. Loads all 0s to all input and DAC registers. Therefore, the outputs also go to 0 V.
2
LDAC
Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. Pulsing this
pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous
update of all DAC outputs. Alternatively, this pin can be tied permanently low.
3
VDD
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 μF
capacitor in parallel with a 0.1 μF capacitor to GND.
4
VOUTA
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
5
VOUTB
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
6
VOUTC
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
7
VREFAB
Reference Input Pin for DAC A and DAC B. It can be configured as a buffered or unbuffered input to each or both of
the DACs, depending on the state of the BUF bits in the serial input words to DAC A and DAC B. It has an input range
of 0.25 V to VDD in unbuffered mode and 1 V to VDD in buffered mode.
8
VREFCD
Reference Input Pin for DAC C and DAC D. It can be configured as a buffered or unbuffered input to each or both of
the DACs, depending on the state of the BUF bits in the serial input words to DAC C and DAC D. It has an input range
of 0.25 V to VDD in unbuffered mode and 1 V to VDD in buffered mode.
9
DCEN
Enables the Daisy-Chaining Option. It should be tied high if the part is being used in a daisy chain, and tied low if it is
being used in standalone mode.
10
PD
Active Low Control Input. It acts like a hardware power-down option. All DACs go into power-down mode when this
pin is tied low. The DAC outputs go into a high impedance state, and the current consumption of the part drops to
300 nA @ 5 V (90 nA @ 3 V).
11
VOUTD
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
12
GND
Ground Reference Point for All Circuitry on the Part.
13
DIN
Serial Data Input. These devices each have a 16-bit shift register. Data is clocked into the register on the falling edge of
the serial clock input. The DIN input buffer is powered down after each write cycle.
14
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be
transferred at rates of up to 30 MHz. The SCLK input buffer is powered down after each write cycle.
15
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers
on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the
following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an interrupt and
the write sequence is ignored by the device.
16
SDO
Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the data in
the shift register for diagnostic purposes. The serial data is transferred on the rising edge of SCLK and is valid on the
falling edge of the clock.


유사한 부품 번호 - AD5327_15

제조업체부품명데이터시트상세설명
logo
Analog Devices
AD5327ARU AD-AD5327ARU Datasheet
585Kb / 28P
   2.5 V to 5.5 V, 400 muA, Quad Voltage Output
REV. C
AD5327ARU-REEL7 AD-AD5327ARU-REEL7 Datasheet
585Kb / 28P
   2.5 V to 5.5 V, 400 muA, Quad Voltage Output
REV. C
AD5327ARUZ AD-AD5327ARUZ Datasheet
585Kb / 28P
   2.5 V to 5.5 V, 400 muA, Quad Voltage Output
REV. C
AD5327BRU AD-AD5327BRU Datasheet
585Kb / 28P
   2.5 V to 5.5 V, 400 muA, Quad Voltage Output
REV. C
AD5327BRU-REEL AD-AD5327BRU-REEL Datasheet
585Kb / 28P
   2.5 V to 5.5 V, 400 muA, Quad Voltage Output
REV. C
More results

유사한 설명 - AD5327_15

제조업체부품명데이터시트상세설명
logo
Analog Devices
AD5307 AD-AD5307_15 Datasheet
585Kb / 28P
   2.5 V to 5.5 V, 400 A, Quad Voltage Output, 8-/10-/12-Bit DACs in 16-Lead TSSOP
REV. C
AD5317 AD-AD5317_15 Datasheet
585Kb / 28P
   2.5 V to 5.5 V, 400 A, Quad Voltage Output, 8-/10-/12-Bit DACs in 16-Lead TSSOP
REV. C
AD5307BRU AD-AD5307BRU Datasheet
585Kb / 28P
   2.5 V to 5.5 V, 400 關A, Quad Voltage Output, 8-/10-/12-Bit DACs in 16-Lead TSSOP
REV. C
AD5308 AD-AD5308_1 Datasheet
575Kb / 24P
   2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
REV. D
AD5318 AD-AD5318_15 Datasheet
408Kb / 28P
   2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
Rev. F
AD5328 AD-AD5328_15 Datasheet
408Kb / 28P
   2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
Rev. F
AD5308 AD-AD5308 Datasheet
308Kb / 19P
   2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
REV. B
AD5308 AD-AD5308_11 Datasheet
408Kb / 28P
   2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
Rev. F
AD5328ARUZ AD-AD5328ARUZ Datasheet
408Kb / 28P
   2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
Rev. F
AD5308 AD-AD5308_15 Datasheet
408Kb / 28P
   2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
Rev. F
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28


데이터시트 다운로드

Go To PDF Page


링크 URL




개인정보취급방침
ALLDATASHEET.CO.KR
ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com