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AD5516 데이터시트(PDF) 11 Page - Analog Devices |
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AD5516 데이터시트(HTML) 11 Page - Analog Devices |
11 / 16 page REV. B AD5516 –11– SYNC must be taken high and low again for further serial data transfer. SYNC may be taken high after the falling edge of the 18th SCLK pulse, observing the minimum SCLK falling edge to SYNC rising edge time, t 6. If SYNC is taken high before the 18th falling edge of SCLK, the data transfer will be aborted and the addressed DAC will not be updated. See the timing diagram in Figure 1. Daisy-Chain Mode (DCEN = 1) I n Daisy-Chain Mode, the internal gating on SCLK is disabled. The SCLK is continuously applied to the input shift register when SYNC is low. If more than 18 clock pulses are applied, the data ripples out of the shift register and appears on the DOUT line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting this line to the DIN input on the next device in the chain, a multidevice interface is constructed. Eighteen clock pulses are required for each device in the system. Therefore, the total number of clock cycles must equal 18N, where N is the total number of devices in the chain. See the timing diagram in Figure 2. When the serial transfer to all devices is complete, SYNC should be taken high. This prevents any further data being clocked into the input shift register. A burst clock containing the exact number of clock cycles may be used and SYNC taken high some time later. After the rising edge of SYNC, data is automatically transferred from each device’s input shift register to the addressed DAC. RESET Function The RESET function on the AD5516 can be used to reset all nodes on this device to their power-on reset condition. This is implemented by applying a low going pulse of 20 ns minimum to the RESET Pin on the device. Table III. Typical Power-On Values Device Output Voltage AD5516-1 –0.073 V AD5516-2 –0.183 V AD5516-3 –0.391 V BUSY Output During conversion, the BUSY output is low and all SCLK pulses are ignored. At the end of a conversion, BUSY goes high indi- cating that the update of the addressed DAC is complete. It is recommended that SCLK is not pulsed while BUSY is low. MICROPROCESSOR INTERFACING The AD5516 is controlled via a versatile 3-wire serial interface that is compatible with a number of microprocessors and DSPs. AD5516 to ADSP-2106x SHARC DSP Interface The ADSP-2106x SHARC DSPs are easily interfaced to the AD5516 without the need for extra logic. The AD5516 expects a t3 (SYNC falling edge to SCLK falling edge setup time) of 15 ns min. Consult the ADSP-2106x User Manual for information on clock and frame sync frequencies for the SPORT Register and contents of the TDIV and RDIV Registers. The user must allow 200 ns (min) between two consecutive Mode 2 writes in Standalone Mode and 400 ns (min) between two consecutive Mode 2 writes in Daisy-Chain Mode. During a Mode 2 operation the BUSY signal remains high. See Figures 4 and 5 for Mode 1 and Mode 2 data formats. When MODE bits = 11, the device is in No Operation mode. This may be useful in daisy-chain applications where the user does not wish to change the settings of the DACs. Simply write 11 to the MODE bits and the following address and data bits will be ignored. SERIAL INTERFACE The AD5516 has a 3-wire interface that is compatible with SPI/QSPI/MICROWIRE, and DSP interface standards. Data is written to the device in 18-bit words. This 18-bit word consists of two mode bits, four address bits, and 12 data bits as shown in Figure 4. The serial interface works with both a continuous and burst clock. The first falling edge of SYNC resets a counter that counts the number of serial clocks to ensure the correct number of bits is shifted in and out of the serial shift registers. In order for another serial transfer to take place, the counter must be reset by the falling edge of SYNC. A3–A0 Four address bits (A3 = MSB Address, A0 = LSB). These are used to address one of 16 DACs. Table II. Selected DAC A3 A2 A1 A0 Selected DAC 0 000 DAC 0 0 001 DAC 1 : ::: 1 111 DAC 15 DB11–DB0 These are used to write a 12-bit word into the addressed DAC register. Figures 1 and 2 show the timing diagram for a write cycle to the AD5516. SYNC FUNCTION In both Standalone and Daisy-Chain Modes, SYNC is an edge- triggered input that acts as a frame synchronization signal and chip enable. Data can only be transferred into the device while SYNC is low. To start the serial data transfer, SYNC should be taken low observing the minimum SYNC falling to SCLK falling edge setup time, t3. Standalone Mode (DCEN = 0) After SYNC goes low, serial data will be shifted into the device’s input shift register on the falling edges of SCLK for 18 clock pulses. After the falling edge of the 18th SCLK pulse, data will automatically be transferred from the input shift register to the addressed DAC. |
유사한 부품 번호 - AD5516_15 |
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유사한 설명 - AD5516_15 |
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