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AD7545BN 데이터시트(PDF) 2 Page - Intersil Corporation |
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AD7545BN 데이터시트(HTML) 2 Page - Intersil Corporation |
2 / 7 page 10-11 Absolute Maximum Ratings Thermal Information Supply Voltage (VDD to DGND) . . . . . . . . . . . . . . . . . . . -0.3V, +17V Digital Input Voltage to DGND . . . . . . . . . . . . . . . .-0.3V, VDD +0.3V VRFB, VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V VPIN1 to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V, VDD +0.3V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V, VDD +0.3V Operating Conditions Temperature Ranges Commercial (J, K, Grades) . . . . . . . . . . . . . . . . . . . . .0oC to 70oC Industrial (A, B, Grades) . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Extended (S Grades) . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Thermal Resistance (Typical, Note 1) θ JA ( oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Maximum Junction Temperature (PDIP Package) . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = See Note 2, VREF = +10V, VOUT1 = 0V, AGND = DGND, Unless Otherwise Specified PARAMETER TEST CONDITIONS VDD = +5V VDD = +15V UNITS MIN TYP MAX MIN TYP MAX STATIC PERFORMANCE Resolution 12 12 Bits Relative Accuracy J, A, S - - ±2- - ±2 LSB K, B - - ±1- - ±1 LSB Differential Nonlinearity J, A, S 10-Bit Monotonic TMIN to TMAX -- ±4- - ±4 LSB K, B 12-Bit Monotonic TMIN to TMAX -- ±1- - ±1 LSB Gain Error (Using Internal RFB) J, A, S DAC Register Loaded with 1111 1111 1111 -- ±20 - - ±25 LSB K, B Gain Error is Adjustable Using the Circuits of Figures 4 and 5 (Note 3) -- ±10 - - ±15 LSB Gain Temperature Coefficient ∆Gain/∆Temperature Typical Value is 2ppm/oC for VDD = +5V (Note 4) -- ±5- - ±10 ppm/oC DC Supply Rejection ∆Gain/∆VDD ∆VDD = ±5% 0.015 - 0.03 0.01 - 0.02 % Output Leakage Current at OUT1 J, K DB0 - DB11 = 0V; WR, CS = 0V (Note 2) - - 50 - - 50 nA A, B - -50- -50 nA S - - 200 - - 200 nA DYNAMIC CHARACTERISTICS Current Setting Time To 1/2 LSB, OUT1 LOAD = 100Ω, DAC Output Measured from Falling Edge of WR, CS = 0V (Note 4) - -2- -2 µs Propagation Delay from Digital Input Change to 90% of Final Analog Output OUT1 LOAD = 100 Ω, CEXT = 13pF (Notes 4 and 5) - - 300 - - 250 ns Digital to Analog Glitch Impulse VREF = AGND - 400 - - 250 - nV/s AC Feedthrough at OUT1 VREF = ±10V, 10kHz Sinewave (Note 6) -5- - 5- mVP-P ANALOG OUTPUTS Output Capacitance COUT1 DB0 - DB11 = 0V, WR, CS = 0V (Note 4) - - 70 - - 70 pF COUT1 DB0 - DB11 = VDD, WR, CS = 0V (Note 4) - - 200 - - 200 pF AD7545 |
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