3-8

4. Calculation of Bias Resistance. For minimum supply

directly from the supplies and not from the bias regulator.

using Ohm’s law.

5. Calculation of Offset Adjustment Circuit. In order to

reduce the loading effect of the offset adjustment circuit

on the power supply, the offset control should be

arranged to provide the necessary offset current. The

source resistance of the non-inverting input is made

equal to the source resistance of the inverting input,

i.e.,

Because the maximum offset voltage is 5mV plus an

additional increment due to the offset current (Figure 2)

±8.6mV. The current necessary to provide this offset is:

With a supply voltage of

±6V, this current can be

provided by a 10M

Ω resistor. However, the stability of

such a resistor is often questionable and a more realistic

value of 2.2M

Ω was used in the final circuit.

Capacitance Effects

The CA3060 is designed to operate at such low power levels

that high impedance circuits must be employed. In designing

such circuits, particularly feedback amplifiers, stray circuit

capacitance must always be considered because of its

adverse effect on frequency response and stability. For

example a 10k

Ω load with a stray capacitance of 15pF has a

time constant of 1MHz. Figure 20 illustrates how a 10k

Ω

15pF load modifies the frequency characteristic.

Capacitive loading also has an effect on slew rate; because

the peak output current is established by the amplifier bias

the maximum rate at which the capacitance can be charged

total load capacitance including strays. This relationship is

shown graphically in Figure 21. When measuring slew rate

for this data sheet, care was taken to keep the total

capacitive loading to 13pF.

Phase Compensation

In many applications phase compensation will not be

required for the amplifiers of the CA3060. When needed,

compensation may easily be accomplished by a simple RC

network at the input of the amplifier as shown in Figure 17.

The values given in Figure 17 provide stable operation for

the critical unity gain condition, assuming that capacitive

loading on the output is 13pF or less. Input phase compen-

sation is recommended in order to maintain the highest

possible slew rate.

In applications such as integrators, two OTAs may be

cascaded to improve current gain. Compensation is best

accomplished in this case with a shunt capacitor at the

output of the first amplifier. The high gain following compen-

sation assures a high slew rate.

R

ABC

V

SUP

V

ABC

–

I

ABC

-------------------------------------

=

R

ABC

12

0.63

–

20

10

6

–

×

-------------------------

=

R

ABC

568.5k

Ω or 560kΩ

≅

=

20k

Ω 200kΩ

×

20k

Ω 200kΩ

+

----------------------------------------

18k

Ω

≅

8.6mV

18k

Ω

------------------

0.48

µA

≅

FREQUENCY (MHz)

0

-20

-40

-60

-80

0.01

0.1

1.0

10

100

FIGURE 20. EFFECT OF CAPACITIVE LOADING ON

FREQUENCY RESPONSE

SLEW RATE (V/

µs)

1000

100

10

1

0.01

0.1

1.0

10

100

A

BCD

E

F

G

H

I

J

K

L

I.

FIGURE 21. EFFECT OF LOAD CAPACITANCE ON SLEW RATE

CA3060