7-85

Specifications CD4014BMS, CD4021BMS

Logic Diagram

FIGURE 1. CD4014BM LOGIC DIAGRAM

Static Burn-In 2 (Note 1)

2, 3, 12

8

1, 4-7, 9-11, 13-6

Dynamic Burn-In (Note 1)

-

1, 4-9, 13 -15

16

2, 3, 12

10

11

Irradiation (Note 2)

2, 3, 12

8

1, 4-7, 9-11, 13-16

NOTE:

1. Each pin except VDD and GND will have a series resistor of 10K

± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 47K

± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD =

10V

± 0.5V

TRUTH TABLE - CD4014BMS

CL

SERIAL INPUT

PARALLEL/SERIAL CONTROL

PI-1

PI-n

Q1 (INTERNAL)

Qn

X

1

0

000

X

1

1

010

X

1

0

101

X

1

1

111

0

0

X

X

0

Qn-1

1

0

X

X

1

Qn-1

X

X

X

X

Q1

Qn

NC

X = Don’t Care Case

NC = No Change

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

(Continued)

FUNCTION

OPEN

GROUND

VDD

9V

± -0.5V

OSCILLATOR

50kHz

25kHz

CL

CL

CL

CL

CL

CL

11

10

9

7

6

5

4

13

14

15

1

P7

P8

P6

P5

P4

P3

P2

P1

P

D

PS

CL

CL

C

CL

CL

PARALLEL/SERIAL

CONTROL

CLOCK

SERIAL

INPUT

P

CL

PS

D

Q

P

CL

PS

D

Q

P

CL

PS

D

Q

CL

PS

P

D

Q

P

CL

PS

D

Q

P

CL

PS

D

Q

P

CL

PS

D

Q

P

CL

PS

D

Q

P

CL

PS

D

Q

*

*

*

p

n

p

n

p

n

p

n

p

n

p

n

Q

VDD

VSS

BY CMOS PROTECTION

NETWORK

≡

3

2

2

Q8

Q7

Q6

********