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ADV7202 데이터시트(PDF) 5 Page - Analog Devices

부품명 ADV7202
상세설명  Simultaneous Sampling Video Rate Codec
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REV. 0
–5–
ADV7202
3.3 V SPECIFICATIONS (AVDD/DVDD = 3.3 V 5%, V
REF = 1.235 V, RSET = 1.2 k
, all specifications TMIN to TMAX
1, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Test Conditions
STATIC PERFORMANCE_DAC
Resolution (Each DAC)
10
Bits
Accuracy (Each DAC)
10
Bits
Integral Nonlinearity
±1
LSB
10-Bit Operation
Differential Nonlinearity
–0.8/0.1
LSB
10-Bit Operation
VIDEO ADC
Resolution
12
Bits
(Including 2 Bits for Gain Ranging)
2.2 V Ref.
Accuracy
12
Bits
Integral Nonlinearity
±4
LSB
12 Bit
Differential Nonlinearity
±1
LSB
12 Bit
Differential Input Voltage Range
2
–VREFADC
+VREFADC
See Table II
SNR
60
dB
27 MHz Clock, fIN = 100 kHz
55
dB
54 MHz Clock
AUX ADC
Resolution
8
Bits
Differential Nonlinearity
±0.5
LSB
Integral Nonlinearity
±0.5
LSB
Input Voltage Range
0
2 VREFADC
V
DIGITAL INPUTS
Input High Voltage, VINH
2V
Input Low Voltage, VINL
0.8
V
Input Current, IIN
±1
µA
Input Capacitance, CIN
10
pF
DIGITAL OUTPUTS
Output High Voltage, VOH
2.4
V
ISOURCE = 400
µA
Output Low Voltage, VOL
0.4
V
ISINK = 1.6 mA
Three-State Leakage Current
10
µA
Output Capacitance
10
pF
Digital Output Access Time, t14
6ns
See Figure 13
Digital Output Hold Time, t15
5ns
ANALOG OUTPUTS
Output Current
4.33
mA
RSET = 1.2 k
Ω, RL = 300 Ω
DAC-to-DAC Matching
4
%
DAC 0, 1, and 2
Output Compliance, VOC
0
1.4
V
Output Impedance, ROUT
50
k
Output Capacitance, COUT
30
pF
IOUT = 0 mA
Analog Output Delay3
5.5
ns
DAC Output Skew
0.06
ns
VOLTAGE REFERENCE
Reference Range, VREFADC
1.100
V
Reference Range, VREFDAC
1.235
V
NOTES
10
°C to 70°C.
2SHA gain = 1, half range for SHA gain = 2, see Table II.
3Output delay measured from 50% of the rising edge of the clock to the 50% point of full-scale transition.
Specifications subject to change without notice.


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