전자부품 데이터시트 검색엔진 |
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ADV7312 데이터시트(PDF) 20 Page - Analog Devices |
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ADV7312 데이터시트(HTML) 20 Page - Analog Devices |
20 / 84 page REV. 0 –20– ADV7312 SR7– SR0 Register Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reset Values HD Output Standard 0 0 EIA770.2 output 00h 01 EIA770.1 output 10 Output levels for full input range 11 Reserved HD Input Control Signals 00 HSYNC, VSYNC, BLANK 01 EAV/SAV codes 10 Async Timing Mode 11 Reserved HD 625p 0 525p 1 625p HD 720p 0 1080i 1 720p HD BLANK Polarity 0 BLANK active high 1 BLANK active low 0 Macrovision off 1 Macrovision on 11h HD Pixel Data Valid 0 Pixel data valid off 00h 1 Pixel data valid on 0 Reserved HD Test Pattern Enable 0 HD test pattern off 1 HD test pattern on 0 Hatch 1 Field/frame HD VBI Open 0 Disabled 1 Enabled HD Undershoot Limiter 00 Disabled 01 –11 IRE 10 –6 IRE 11 –1.5 IRE HD Sharpness Filter 0 Disabled 1 Enabled 00 00 clk cycles 00 11 clk cycles 01 02 clk cycles 01 13 clk cycles 10 04 clk cycles 00 0 0 clk cycles 00 1 1 clk cycle 01 0 2 clk cycles 01 1 3 clk cycles 10 0 4 clk cycles HD CGMS 0 Disabled 1 Enabled 0 Disabled 1 Enabled 12h HD Mode Register 3 HD Y Delay with Respect to Falling Edge of HSYNC HD Color Delay with Respect to Falling Edge of HSYNC HD CGMS CRC HD Mode Register 1 10h HD Test Pattern Hatch/Field HD Macrovision for 525p/625p HD Mode Register 2 00h |
유사한 부품 번호 - ADV7312_15 |
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유사한 설명 - ADV7312_15 |
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