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HD74LV125ARPEL 데이터시트(PDF) 3 Page - Renesas Technology Corp |
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3 / 12 page Rev.3.00 Jun. 03, 2004 page 1 of 9 HD74LV125A Quad. Bus Buffer Gates with 3-state Outputs REJ03D0315–0300Z (Previous ADE-205-245A (Z)) Rev.3.00 Jun. 03, 2004 Description The HD74LV125A features independent line drivers with three state outputs. Each output is disabled when the associated output enable ( OE) input is high. To ensure the high impedance state during power up or power down, OE should be connected to VCC through a pull-down resistor; the minimum value of the resistor is determined by the current souring capability of the driver. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life. Features • V CC = 2.0 V to 5.5 V operation • All inputs V IH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) • All outputs V O (Max.) = 5.5 V (@VCC = 0 V) • Typical V OL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) • Typical V OH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) • Output current ±8 mA (@V CC = 3.0 V to 3.6 V), ±16 mA (@VCC = 4.5 V to 5.5 V) • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74LV125AFPEL SOP–14 pin(JEITA) FP–14DAV FP EL (2,000 pcs/reel) HD74LV125ARPEL SOP–14 pin(JEDEC) FP–14DNV RP EL (2,500 pcs/reel) HD74LV125ATELL TSSOP–14 pin TTP–14DV T ELL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs OE A Output Y LH H LL L HX Z Note: H: High level L: Low level X: Immaterial Z: High impedance |
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