DEVICES INCORPORATED

LF43168

Dual 8-Tap FIR Filter

4

Video Imaging Products

03/28/2000–LDS.43168-H

ACCEN — Accumulate Enable

When ACCEN is HIGH, both accumu-

lators are enabled for accumulation

and writing to the accumulator output

registers is disabled (the registers hold

their values). When ACCEN goes

LOW, accumulation is halted (by

sending zeros to the accumulator

feedback inputs) and writing to the

accumulator output registers is

enabled. This signal is latched on the

rising edge of CLK.

shown in Table 3. Data is latched on

the rising edge of CLK.

OEL — Output Enable Low

is available for data input.

OEH — Output Enable High

enabled for output. When OEH is

impedance state.

FUNCTIONAL DESCRIPTION

Control Registers

There are two control registers which

determine how the LF43168 is config-

ured. Tables 1 and 2 show how each

is latched into the addressed control

register on the rising edge of WR.

trol Register 0 is written to using

address 000H. Control Register 1 is

written to using address 001H (Note

that addresses 002H to 0FFH are

reserved and should not be written

to). When a control register is written

to, a reset occurs which lasts for 6 CLK

cycles from when WR goes HIGH.

This reset does not alter any data in

the coefficient banks. Control data

can be loaded asynchronously to CLK.

Bits 0-3 of Control Register 0 control

the decimation registers. The decima-

tion factor and decimation register

delay length is set using these bits.

Bit 4 determines if FIR filters A and B

operate separately as two filters or

together as one filter. Bit 5 is used to

select even or odd-symmetric coeffi-

cients. Bits 6 and 7 determine if there

are an even or odd number of taps in

filters A and B respectively. When the

FIR filters are set to operate as two

separate filters, bit 8 selects either

source. Bit 9 determines if the coeffi-

cient set used is interleaved or non-

interleaved (see Interleaved Coeffi-

cient Filters section). Most applica-

tions use non-interleaved coefficient

sets (bit 9 set to “0”).

Bits 0 and 1 of Control Register 1

determine the input and coefficient

data formats respectively for filter A.

Bits 2 and 3 determine the input and

coefficient data formats respectively

for filter B. Bit 4 is used to enable or

disable data reversal on the reverse

decimation path. When data reversal

is enabled, the data order is reversed

before being sent to the reverse

decimation path. Bits 5-8 select where

rounding will occur on the output

data (See Mux/Adder section). Bit 9

enables or disables output rounding.

Coefficient Banks

The coefficient banks supply coeffi-

cient data to the multipliers in both

FIR filters. The LF43168 can store 32

different coefficient sets. A coefficient

BITS

FUNCTION

DESCRIPTION

0–3

Decimation Factor/

0000 = No Decimation, Delay by 1

Decimation Register Delay Length 0001 = Decimate by 2, Delay by 2

0010 = Decimate by 3, Delay by 3

0011 = Decimate by 4, Delay by 4

0100 = Decimate by 5, Delay by 5

0101 = Decimate by 6, Delay by 6

0110 = Decimate by 7, Delay by 7

0111 = Decimate by 8, Delay by 8

1000 = Decimate by 9, Delay by 9

1001 = Decimate by 10, Delay by 10

1010 = Decimate by 11, Delay by 11

1011 = Decimate by 12, Delay by 12

1100 = Decimate by 13, Delay by 13

1101 = Decimate by 14, Delay by 14

1110 = Decimate by 15, Delay by 15

1111 = Decimate by 16, Delay by 16

4

Filter Mode Select

0 = Single Filter Mode

1 = Dual Filter Mode

5

Coefficient Symmetry Select

0 = Even-Symmetric Coefficients

1 = Odd-Symmetric Coefficients

6

FIR Filter A: Odd/Even Taps

0 = Odd Number of Filter Taps

1 = Even Number of Filter Taps

7

FIR Filter B: Odd/Even Taps

0 = Odd Number of Filter Taps

1 = Even Number of Filter Taps

8

FIR Filter B Input Source

9

Interleaved/Non-Interleaved

0 = Non-Interleaved Coefficient Sets

Coefficient Sets

1 = Interleaved Coefficient Sets