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LF43168QC15 데이터시트(PDF) 5 Page - LOGIC Devices Incorporated |
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LF43168QC15 데이터시트(HTML) 5 Page - LOGIC Devices Incorporated |
5 / 16 page DEVICES INCORPORATED Video Imaging Products 5 LF43168 Dual 8-Tap FIR Filter 03/28/2000–LDS.43168-H set consists of 8 coefficient values. Each bank can hold 32 10-bit values. CSEL4-0 is used to select which coefficient set is sent to the filter multipliers. The coefficient set fed to the multipliers may be switched every CLK cycle if desired. Data on CIN9-0 is latched into the addressed coefficient bank on the rising edge of WR. Address data is input on A8-0 and is decoded as follows: A1-0 determines the bank number (“00”, “01”, “10”, and “11” correspond to banks 0, 1, 2, and 3 respectively), A2 determines which filter (“0” = filter A, “1” = filter B), A7-3 determines which set number the coefficient is in, and A8 must be set to “1”. For example, an address of “100111011” will load coefficient set 7 in bank 3 of filter A with data. Coeffi- cient data can be loaded asynchro- nously to CLK. Decimation Registers The decimation registers are provided to take advantage of symmetric filter coefficients and to provide data storage for 2-D filtering. The outputs of the registers are fed into the ALUs. Both inputs to an ALU need to be multiplied by the same filter coeffi- cient. By adding or subtracting the two data inputs together before being sent to the filter multiplier, the num- ber of filter taps needed is cut in half. Therefore, an 8-tap FIR filter can be made with only four multipliers. The decimation registers are divided into two groups, the forward and reverse decimation registers. As can be seen in Figure 1, data flows left to right through the forward decimation registers and right to left through the reverse decimation registers. The decimation registers can be pro- BITS FUNCTION DESCRIPTION 0 FIR Filter A Input Data Format 0 = Unsigned 1 = Two’s Complement 1 FIR Filter A Coefficient Format 0 = Unsigned 1 = Two’s Complement 2 FIR Filter B Input Data Format 0 = Unsigned 1 = Two’s Complement 3 FIR Filter B Coefficient Format 0 = Unsigned 1 = Two’s Complement 4 Data Order Reversal Enable 0 = Enabled 1 = Disabled 5–8 Output Round Position 0000 = 2–10 0001 = 2–9 0010 = 2–8 0011 = 2–7 0100 = 2–6 0101 = 2–5 0110 = 2–4 0111 = 2–3 1000 = 2–2 1001 = 2–1 1010 = 20 1011 = 21 9 Output Round Enable 0 = Enabled 1 = Disabled TABLE 2. CONTROL REGISTER 1 – ADDRESS 001H grammed to decimate by 2 to 16 (see Decimation section and Table 1). SHFTEN enables and disables the shifting of data through the decima- tion registers. When SHFTEN is LOW, data on INA9-0 and INB9-0 can be latched into the device and data can be shifted through the decimation registers. When SHFTEN is HIGH, data on INA9-0 and INB9-0 can not be latched into the device and data in the input and decimation registers is held. Data feedback circuitry is positioned between the forward and reverse decimation registers. It controls how data from the forward decimation path is fed to the reverse decimation path. The feedback circuitry can either reverse the data order or pass the data unchanged to the reverse decimation path. The mux/demux sends incoming data to one of the LIFOs or the data feedback decimation register. The LIFOs and decimation register feed into a mux. This mux determines if one of the LIFOs or the decimation register sends data to the reverse decimation path. If the data order needs to be reversed before being sent to the reverse decimation path (for example, when decimating), Data Reversal Mode should be enabled by setting bit 4 of Control Register 1 to “0”. When Data Reversal is enabled, data from the forward decimation path is written into one of the LIFOs in the data feedback section while the other LIFO sends data to the reverse decimation path. When TXFR goes LOW, the LIFO sending data to the reverse decimation path becomes the LIFO receiving data from the forward decimation path, and the LIFO receiving data from the forward decimation path becomes the LIFO sending data to the reverse decimation path. The device must see a HIGH to LOW transition of TXFR in order to switch LIFOs. The size of data blocks sent to the reverse decimation path is determined by how often TXFR goes LOW. To send data blocks of size 8 to |
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