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MGA-31389 데이터시트(PDF) 1 Page - AVAGO TECHNOLOGIES LIMITED

부품명 MGA-31389
부품 상세설명  0.1W High Gain Driver Amplifier
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제조업체  AVAGO [AVAGO TECHNOLOGIES LIMITED]
홈페이지  http://www.avagotech.com
Logo AVAGO - AVAGO TECHNOLOGIES LIMITED

MGA-31389 데이터시트(HTML) 1 Page - AVAGO TECHNOLOGIES LIMITED

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MGA-31389
0.1W High Gain Driver Amplifier
50MHz ~ 2GHz
Data Sheet
Description
Avago Technologies MGA-31389 is a high performance
Driver Amplifier MMIC, housed in a standard SOT-89 plastic
package. The device features flat high gain with excellent
input and output return loss, as well as superior linearity
performance. The device can be easily matched to obtain
desired performance.
MGA-31389 is especially ideal for 50
Ω wireless infrastruc-
ture application within the 50 MHz to 2GHz frequency
range applications. With high IP3 and low noise figure and
wideband operation, the MGA-31389 may be utilized as
a driver amplifier in the transmit chain and as a second
stage LNA in the receiver chain.
This device uses Avago Technologies proprietary 0.25
mm
GaAs Enhancement mode PHEMT process.
Pin connections and Package Marking
Note:
Package marking provides orientation and identification
“13” = Device Code
“X” = Date Code character indentifies month of manufacturing
Features
• ROHS compliant
• Halogen free
• High IP3 at low DC bias power(1)
• High gain, with good gain flatness
• Low noise figure
• Advanced enhancement mode PHEMT Technology
• Excellent uniformity in product specification
• SOT-89 standard package
Specifications
At 0.9 GHz, Vd = 5 V, Id = 73 mA (typ) @ 25° C
• OIP3 = 38.6 dBm
• Noise Figure = 2.0 dB
• Gain = 21.3 dB, Gain flatness (± 50 MHz) = 0.14 dB
• P1dB = 22.2 dBm
• IRL = 30.5 dB, ORL = 14.7 dB
Note:
1. The MGA-31389 has a superior LFOM of 13.3 dB. Linearity Figure of
Merit (LFOM) is essentially OIP3 divided by DC bias power.
Simplified Schematic
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 75 V
ESD Human Body Model = 1000 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
Figure 1. Simplified Schematic diagram
L
RFout
C
C
RFin
Vdd
C
C
C
13X
Top View
RFin
GND
RFout
#1
#2
#3
Bottom View
RFout
GND
RFin
#3
#2
#1


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