3.5- and 4.5-Digit, Single-Chip ADCs with LED

Drivers and µC Interface

6

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TIMING CHARACTERISTICS (Notes 11, 12, Figure 8)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SCLK Operating Frequency

0

4.2

MHz

SCLK Pulse-Width High

100

ns

SCLK Pulse-Width Low

100

ns

DIN to SCLK Setup

50

ns

DIN to SCLK Hold

0ns

CS Fall to SCLK Rise Setup

50

ns

SCLK Rise to CS Rise Hold

0ns

SCLK Fall to DOUT Valid

120

ns

CS Rise to DOUT Disable

120

ns

CS Fall to DOUT Enable

120

ns

Note 1: Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after nulling the gain error and

offset error.

Note 2: Offset calibrated. See OFFSET_CAL1 and OFFSET_CAL2 (MAX1499 only) in the On-Chip Registers section.

Note 3: Offset nulled.

Note 4: Offset drift error is eliminated by recalibration at the new temperature.

Note 5: The input voltage range for the analog inputs is given with respect to the voltage on the negative input of the differential pair.

AIN+ and REF+ only.

Note 7: Measured at DC by changing the power-supply voltage from 2.7V to 5.25V and measuring the effect on the conversion

error with external reference. PSRR at 50Hz and 60Hz exceeds 120dB with filter notches at 50Hz and 60Hz (Figure 2).

Note 8: CLK and SCLK are disabled.

Note 9: LED drivers are disabled.

Note 12: See the serial-interface timing diagrams.