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74CBTLVD3861 데이터시트(PDF) 11 Page - NXP Semiconductors |
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74CBTLVD3861 데이터시트(HTML) 11 Page - NXP Semiconductors |
11 / 19 page 74CBTLVD3861 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 — 14 December 2011 11 of 19 NXP Semiconductors 74CBTLVD3861 10-bit level-shifting bus switch with output enable Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 16. Test circuit for measuring switching times VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aae331 VEXT VCC VI VO DUT CL RT RL RL G Table 10. Test data Supply voltage Load VEXT VCC CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 3.0 V to 3.6 V 30 pF 1 k open GND 3.6 V |
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