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74LVCH32244A 데이터시트(PDF) 3 Page - NXP Semiconductors |
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3 / 14 page 74LVCH32244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 16 December 2011 3 of 14 NXP Semiconductors 74LVCH32244A 32-bit buffer/line driver; 5 V input/output tolerant; 3-state 5. Pinning information 5.1 Pinning 5.2 Pin description Fig 3. Pin configuration mna471 1A1 1A3 2A1 2A3 3A1 3A3 4A1 4A2 5A1 5A3 6A1 6A3 7A1 7A3 8A1 8A2 1A0 1A2 2A0 2A2 3A0 3A2 4A0 4A3 5A0 5A2 6A0 6A2 7A0 7A2 8A0 8A3 1Y0 1Y2 2Y0 2Y2 3Y0 3Y2 4Y0 4Y3 5Y0 5Y2 6Y0 6Y2 7Y0 7Y2 8Y0 8Y3 1Y1 1Y3 2Y1 2Y3 3Y1 3Y3 4Y1 4Y2 5Y1 5Y3 6Y1 6Y3 7Y1 7Y3 8Y1 8Y2 2OE 3OE 6OE GND GND GND GND 7OE VCC VCC GND GND GND GND VCC VCC 1OE 6 5 2 1 4 3 4OE 5OE GND GND GND GND 8OE VCC VCC GND GND GND GND VCC VCC AH J BD E G T CF K M N R LP Table 2: Pin description Symbol Ball Description nOE (n = 1 to 8) A3, A4, H4, H3, J3, J4, T4, T3 3-state output enable input (active LOW) 1A[0:7] A5, A6, B5, B6 data input 2A[0:7] C5, C6, D5, D6 3A[0:7] E5, E6, F5, F6 4A[0:7] G5, G6, H6, H5 5A[0:7] J5, J6, K5, K6 6A[0:7] L5, L6, M5, M6 7A[0:7] N5, N6, P5, P6 8A[0:7] R5, R6, T6, T5 1Y[0:7] A2, A1, B2, B1 data output 2Y[0:7] C2, C1, D2, D1 3Y[0:7] E2, E1, F2, F1 4Y[0:7] G2, G1, H1, H2 5Y[0:7] J2, J1, K2, K1 6Y[0:7] L2, L1, M2, M1 7Y[0:7] N2, N1, P2, P1 8Y[0:7] R2, R1, T1, T2 GND B3, B4, D3, D4, E3, E4, G3, G4, K3, K4, M3, M4, N3, N4, R3, R4 ground (0 V) VCC C3, C4, F3, F4, L3, L4, P3, P4 supply voltage |
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