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TM114

Rev:1.4

Date: October 24, 2011

© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice

STC5423

Synchronous Clock for SETS

Data sheet

Table of Contents

STC5423 Pin Diagram (Top View) .................................................................................................................... 5

STC5423 Pin Description .................................................................................................................................. 6

Register Map ..................................................................................................................................................... 9

Master Clock Frequency .................................................................................................................................. 11

Input and Output Frequencies

....................................................................................................................... 12

Clock Output Jitter ........................................................................................................................................... 13

General Description ......................................................................................................................................... 14

Application ............................................................................................................................................... 14

Overview .................................................................................................................................................. 14

Chip Master Clock .................................................................................................................................... 14

Reference Inputs ...................................................................................................................................... 14

Timing Generator and Operation Mode ................................................................................................... 14

Phase Synchronization ............................................................................................................................ 15

Clock Outputs .......................................................................................................................................... 15

Redundant Design ................................................................................................................................... 15

Control Interfaces ..................................................................................................................................... 15

Field Upgradability ................................................................................................................................... 15

Advantage and Performance ................................................................................................................... 15

Detailed Description ......................................................................................................................................... 17

Chip Master Clock .................................................................................................................................... 17

Freerun Clock .......................................................................................................................................... 17

Operation Mode ....................................................................................................................................... 17

PLL Event In ............................................................................................................................................ 18

Frequency and Phase Transient .............................................................................................................. 18

Frequency Transient ........................................................................................................................ 18

Phase Transient ............................................................................................................................... 18

History of Fractional Frequency Offset .................................................................................................... 18

Short-Term History ........................................................................................................................... 18

Long-Term History ............................................................................................................................ 19

Device Holdover History ................................................................................................................... 19

User-Specified History ...................................................................................................................... 19

Phase-Locked Loop Status Details .......................................................................................................... 19

Reference Inputs Details .......................................................................................................................... 19

Input Frequency and Frequency Offset Detection ........................................................................... 20

Activity Monitoring ............................................................................................................................ 20

Input Qualification ............................................................................................................................ 20

Automatic Reference Election Mechanism ...................................................................................... 21

Automatic Reference Selection ........................................................................................................ 21

Manual Reference Selection Mode .................................................................................................. 22

Hard-Wired Manual Reference Selection ......................................................................................... 22

Clock Outputs Details .............................................................................................................................. 22

Clock Synthesizers ........................................................................................................................... 22

Clock Generators ............................................................................................................................. 22

Clock Output Phase Alignment ........................................................................................................ 23

Synthesizer Skew Programming ...................................................................................................... 23

Clock Outputs ................................................................................................................................... 23

Redundant Application ............................................................................................................................. 23

Multiple Master Configuration .......................................................................................................... 23

Event Interrupts ........................................................................................................................................ 23