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S1142C 데이터시트(PDF) 11 Page - Seiko Instruments Inc |
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S1142C 데이터시트(HTML) 11 Page - Seiko Instruments Inc |
11 / 32 page HIGH-WITHSTAND VOLTAGE LOW CURRENT CONSUMPTION LOW DROPOUT CMOS VOLTAGE REGULATOR Rev.1.2_00 S-1142C/D Series Seiko Instruments Inc. 11 Standard Circuit CIN *1 CL *2 Input Output GND Single GND VOUT VIN VSS ON / OFF *1. CIN is a capacitor for stabilizing the input. *2. A ceramic capacitor of 0.1 μF or more can be used as CL. Figure 10 Caution The above connection diagram and constants will not guarantee successful operation. Perform thorough evaluation using an actual application to set the constants. Condition of Application Input capacitor (CIN): 0.1 μF or more Output capacitor (CL): 0.1 μF or more Caution Generally a series regulator may cause oscillation, depending on the selection of external parts. Confirm that no oscillation occurs in the application for which the above capacitors are used. Selection of Input and Output Capacitors (CIN, CL) The S-1142C/D Series requires an output capacitor between the VOUT pin and the VSS pin for phase compensation. Operation is stabilized by a ceramic capacitor with an output capacitance of 0.1 μF or more over the entire temperature range. When using an OS capacitor, a tantalum capacitor, or an aluminum electrolytic capacitor, the capacitance must be 0.1 μF or more. The values of output overshoot and undershoot, which are transient response characteristics, vary depending on the value of the output capacitor. The required value of capacitance for the input capacitor differs depending on the application. Set the value for input capacitor (CIN) and output capacitor (CL) as follows. CIN ≥ 0.1 μF CL ≥ 0.1 μF Caution Define the capacity values of CIN and CL by sufficient evaluation including the temperature characteristics under the actual usage conditions. |
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