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ISL22326UFR16Z 데이터시트(PDF) 1 Page - Intersil Corporation |
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ISL22326UFR16Z 데이터시트(HTML) 1 Page - Intersil Corporation |
1 / 17 page 1 FN6176.3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas LLC. Copyright Intersil Americas LLC. 2006, 2008, 2009, 2015. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL22326 Dual Digitally Controlled Potentiometers (XDCP™) Low Noise, Low Power, I2C™ Bus, 128 Taps The ISL22326 integrates two digitally controlled potentiometers (XDCP) and non-volatile memory on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. Each potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. At power-up the device recalls the contents of the two DCP’s IVR to the corresponding WRs. The DCPs can be used as three-terminal potentiometers or as two-terminal variable resistors in a wide variety of applications including control, parameter adjustments, and signal processing. Features • Two potentiometers in one package • 128 resistor taps •I2C serial interface - Three address pins, up to eight devices/bus • Non-volatile storage of wiper position • Wiper resistance: 70 typical @ VCC = 3.3V • Shutdown mode • Shutdown current 5µA max • Power supply: 2.7V to 5.5V •50k or 10k total resistance • High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T < +55°C • 14 Ld TSSOP or 16 Ld QFN package • Pb-free (RoHS compliant) Pinouts ISL22326 (14 LD TSSOP) TOP VIEW ISL22326 (16 LD QFN) TOP VIEW A2 1 2 3 4 5 6 7 SDA SCL 8 9 10 14 13 12 11 SHDN RW0 RL0 RH0 A1 VCC RW1 RL1 RH1 A0 GND NC NC RW1 RH1 RL0 RL1 RH0 RW0 1 3 4 15 16 14 13 2 12 10 9 11 6 57 8 Data Sheet September 9, 2015 |
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