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SM3320A 데이터시트(PDF) 8 Page - Nippon Precision Circuits Inc |
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SM3320A 데이터시트(HTML) 8 Page - Nippon Precision Circuits Inc |
8 / 15 page SM3320A SEIKO NPC CORPORATION - 8 FUNCTIONAL DESCRIPTION Basic Function The SM3320A detects the current generated from a photodiode and outputs a voltage signal. The transimpedance of the preamplifier can be adjusted for coarse adjustment of the sensitivity. The transimpedance adjustment range is 0.5MΩ to 60MΩ, set using 4 adjustment bits. Also, a dark current compensation circuit is used to compensate photodiode output under dark lighting conditions for output voltage stability with low temperature variation. The gain of the postamplifier can be adjusted for fine adjustment of the sensitivity. The gain adjustment range is 1 to 4 times, set using 4 adjustment bits. Also, a built-in offset cancel circuit is used to provide low offset voltage at the output. The output voltage at the time of optical irradiation nothing outputs 0.1VDD, and calls this dark voltage. The maximum output voltage at the time of optical irradiation is 0.7VDD. The device can be addressed using address pin control. This function allows the transimpedance and gain settings to be adjusted for each device independently, when multiple devices are connected in parallel.An output enable control (OE) is used for output control. [Address andA[2:0] setting] Address A2 setting A1 setting A0 setting [000] VSS VSS VSS [001] VSS VSS VDD [010] VSS VDD VSS [011] VSS VDD VDD [100] VDD VSS VSS [101] VDD VSS VDD [110] VDD VDD VSS [111] VDD VDD VDD Serial Interface The SM3320Ause a 3-wire serial interface (SE, CLK, DATA) to access the device and to set an internal register to control device operation. Note that extraneous signal input on the serial interface pins must be avoided when not reading/writing data to the device to prevent incorrect operation. Internal Register Structure The device read/write mode, address, preamplifier transimpedance, and postamplifier gain are set in the internal register. The device can be accessed for writing data to the register when theA[2:0] address write data bits match the setting of the address control inputs (A2 toA0). RW A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ---- CS1 CS0 TS1 TS0 GS3 GS2 GS1 GS0 Preamplifier transimpedance Postamplifier gain Feedback capacitance Conversion time R/W Data Adress Don't care (1) RW Read/Write mode set bit. Set to “1” for read mode, and to “0” for write mode. (2)AddressA[2:0] (A2 toA0) Address bits. (3) Preamplifier transimpedance CS[1:0] (D7 to D6) and TS[1:0] (D5 to D4) Preamplifier transimpedance setting bits (4) Postamplifier gain GS[3:0] (D3 to D0) Postamplifier gain setting bits Adress Address Address |
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