LM25119/25119Q

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SNVS680G – AUGUST 2010 – REVISED JANUARY 2014

Pin Functions

Pin Descriptions

Pin

Name

Description

1

VCC1

Bias supply pin. Locally decouple to PGND1 using a low ESR/ESL capacitor located as close to

controller as possible.

2

LO1

Low side MOSFET gate drive output. Connect to the gate of the channel1 low-side synchronous

MOSFET through a short, low inductance path.

3

PGND1

Power ground return pin for low side MOSFET gate driver. Connect directly to the low side of the

channel1 current sense resistor.

4

CSG1

Kelvin ground connection to the external current sense resistor. Connect directly to the low side of the

channel1 current sense resistor.

5

CS1

Current sense amplifier input. Connect to the high side of the channel1 current sense resistor.

6

RAMP1

PWM ramp signal. An external resistor and capacitor connected between the SW1 pin, the RAMP1 pin

and the AGND pin sets the channel1 PWM ramp slope. Proper selection of component values

produces a RAMP1 signal that emulates the current in the buck inductor.

7

SS1

An external capacitor and an internal 10 µA current source set the ramp rate of the channel1 error amp

reference. The SS1 pin is held low when VCC1 or VCC2 < 4 V, UVLO < 1.25 V or during thermal

shutdown.

8

VCCDIS

Optional input that disables the internal VCC regulators when external biasing is supplied. If VCCDIS

>1.25 V, the internal VCC regulators are disabled. The externally supplied bias should be coupled to

the VCC pins through a diode. VCCDIS has a 500 k

Ω pull-down resistor to ground to enable the VCC

regulators when the pin is left floating. The pull-down resistor can be overridden by pulling VCCDIS

above 1.25 V with a resistor divider connected to the external bias supply.

9

FB1

Feedback input and inverting input of the channel1 internal error amplifier. A resistor divider from the

channel1 output to this pin sets the output voltage level. The regulation threshold at the FB1 pin is 0.8

V.

10

COMP1

Output of the channel1 internal error amplifier. The loop compensation network should be connected

between this pin and the FB1 pin.

11

EN2

If the EN2 pin is low, channel2 will be disabled. Channel1 and all other functions remain active. The

EN2 has a 50 k

Ω pull-up resistor to enable channel2 when the pin is left floating.

12

AGND

Analog ground. Return for the internal 0.8 V voltage reference and analog circuits.

13

RT

The internal oscillator is set with a single resistor between RT and AGND. The recommended

maximum oscillator frequency is 1.5 MHz which corresponds to a maximum switching frequency of 750

kHz for either channel. The internal oscillator can be synchronized to an external clock by coupling a

positive pulse into RT through a small coupling capacitor.

14

RES

The restart timer pin for an external capacitor that configures the hiccup mode current limiting. A

capacitor on the RES pin determines the time the controller will remain off before automatically

restarting in hiccup mode. The two regulator channels operate independently. One channel may

operate in normal mode while the other is in hiccup mode overload protection. The hiccup mode

commences when either channel experiences 256 consecutive PWM cycles with cycle-by-cycle current

limiting. After this occurs, a 10 µA current source charges the RES pin capacitor to the 1.25 V

threshold which restarts the overloaded channel.

15

COMP2

Output of the channel2 internal error amplifier. The loop compensation network should be connected

between this pin and the FB2 pin.

16

FB2

Feedback input and inverting input of the channel2 internal error amplifier. A resistor divider from the

channel2 output to this pin sets the output voltage level. The regulation threshold at the FB2 pin is 0.8

V.

17

DEMB

Logic input that enables diode emulation when in the low state. In diode emulation mode, the low side

MOSFET is latched off for the remainder of the PWM cycle when the buck inductor current reverses

direction (current flow from output to ground). When DEMB is high, diode emulation is disabled

allowing current to flow in either direction through the low side MOSFET. A 50 k

Ω pull-down resistor

internal to the LM25119 holds DEMB pin low and enables diode emulation if the pin is left floating.

18

SS2

An external capacitor and an internal 10 µA current source set the ramp rate of the channel2 error amp

reference. The SS2 pin is held low when VCC1 or VCC2 < 4 V, UVLO < 1.25 V or during thermal

shutdown.

19

RAMP2

PWM ramp signal. An external resistor and capacitor connected between the SW2 pin, the RAMP2 pin

and the AGND pin sets the channel2 PWM ramp slope. Proper selection of component values

produces a RAMP2 signal that emulates the current in the buck inductor.

20

CS2

Current sense amplifier input. Connect to the high side of the channel2 current sense resistor.

21

CSG2

Kelvin ground connection to the external current sense resistor. Connect directly to the low side of the

channel2 current sense resistor.

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