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TLE7273-2 데이터시트(PDF) 9 Page - Infineon Technologies AG

부품명 TLE7273-2
상세설명  Low Dropout Voltage Regulator
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제조업체  INFINEON [Infineon Technologies AG]
홈페이지  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

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Data Sheet
9
Rev. 1.21, 2014-11-19
TLE7273-2
Block Description and Electrical Characteristics
is in the very first turn after power up a long open window with tmax = 4 *
t
OW. In the following turns, the timing
corresponds to the standard timing setting as described in the specification.
When a valid trigger signal is detected during the open window a closed window is initialized immediately. A trigger
signal within the closed window is interpreted as a pretrigger failure and results in a reset. After the closed window
the open window with the duration
t
OW is started again. The open window lasts at minimum until the trigger process
has occurred, at maximum
t
OW is 32 ms (typ. value with fast timing).
A HIGH to LOW transition of the watchdog trigger signal at pin WDI is considered as a valid trigger pulse.
See Figure 7: To avoid wrong triggering due to parasitic glitches two HIGH samples followed by two LOW samples
(sample period
t
sam typ. 0.5 ms) are decoded as a valid trigger .
A reset is generated (RO goes LOW) if there is no trigger pulse during the open window or if a pretrigger occurs
during the closed window. The triggering is correct also, if the first three samples (two HIGH one LOW) of the
trigger pulse at pin WDI are inside the closed window and only the fourth sample (the second LOW sample) is
taken in the open window.
After turning OFF the Watchdog by output current reduction, RO remains high. (see also the signal diagram in
Figure 6). After turning ON the WWD again by exceeding the current threshold, the logic cycle starts again with
the Ignore Window and goes then into the “1st. long open window”. This 1st long OW is maximum 4 *
t
OW long and
allows the re-synchronisation between the micro controller and the WWD timing. The 1st. long OW is closed by
the first valid trigger on WDI from the mirco controller. This trigger ensures the synchronisation. As soon as this
trigger is done, the micro controller timing must be stable and correspondent to
t
WD.
Figure 5
Window Watchdog State Diagram, Watchdog and Reset Modes
AEA03527_1.VSD
No Trigger
Closed
Window
Open
Window
Trigger
WM1
LLH
H
WM2
L
H
L
H
Window Watchdog Mode
Fast
Slow
Fast
Off
Reset
Trigger
Ignore
Window
Always
Always
No Trigger During
Open Window
Trigger During
Closed Window
Reset Mode
Fast
Slow
Slow
Slow
Watchdog
OFF
IQ > 5mA
Always
IQ < 0.5mA


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