sleep

wake

0.6V

2.5 2A

+

-

0.9V

V clamp

+

-

+

-

SS

logic

+

-

TSD

VDD_low

ss end

blanking

qn

qn

fpwm

Sync and

bootstrap

control

fpwm

Sync

Sync

5 2A

VDD_low

EN

FB

SW

SW

FPWM

COMP

PGOOD

SS

AGND

SYNC

BOOT

VIN

VBIAS

VDD

AVIN

SD

+

-

+

-

+

-

Clock / Sync

BG

BG

+

I Sense

PWM

Comp

BG

IREF

TSD

FPWM / Sleep

Peak Current

Control

Sleep

Reset

EA

PG

0.92BG

+

-

Corrective

Ramp

PWM Control

Logic

+

-

+

-

Sleep

Set

LDO

UVLO

on

Switchover

control

VREG

sleep

EP

frequency

foldback

FREQ

soft start

on

SD

ff

ff

PGND

1 2s/DIV

Vout

10 mV/Div

IL

500 mA/Div

ID

1A/Div

5V/Div

LM26003, LM26003-Q1

SNVS576F – AUGUST 2008 – REVISED FEBRUARY 2015

www.ti.com

8 Detailed Description

8.1 Overview

The LM26003 device is a current mode PWM buck regulator. At the beginning of each clock cycle, the internal

high-side switch turns on, allowing current to ramp-up in the inductor. The inductor current is internally monitored

during each switching cycle. A control signal derived from the inductor current is compared to the voltage control

signal at the COMP pin, derived from the feedback voltage. When the inductor current reaches its threshold, the

high-side switch is turned off and inductor current ramps-down. While the switch is off, inductor current is

supplied through the catch diode. This cycle repeats at the next clock cycle. In this way, duty-cycle and output

voltage are controlled by regulating inductor current. Current mode control provides superior line and load

regulation. Other benefits include cycle-by-cycle current limiting and a simplified compensation scheme. Typical

PWM waveforms are shown in Figure 10.

Figure 10. PWM Waveforms 1A-Load, Vin = 12 V

8.2 Functional Block Diagram

10

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