ML2252, ML2259

10

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies,

create distortion products, of order (m + n), at sum and

3,... . Intermodulation terms are those for which m or n is

not equal to zero. The (IMD) intermodulation distortion

1.7 DIGITAL INTERFACE

The analog inputs are selected by the digital addresses,

ADDR0–ADDR2, and latched on the rising edge of ALE.

This is described in the Multiplexer Addressing section.

A conversion is initiated by the rising edge of a START

pulse. As long as this pulse is high, the internal logic is

reset.

The sampling interval starts with the following CLK rising

edge after a START falling edge and ends on the falling

edge of CLK. The conversion starts and EOC goes low. The

sampling clock is at least one half CLK period wide. Each

bit conversion in the successive approximation process

takes 1 CLK period. On the rising edge of the ninth CLK

pulse, the digital output of the conversion is updated on

the outputs DB0–DB7 and EOC goes high indicating the

conversion is done and data on DB0–DB7 is valid.

One feature of the ML2252 and ML2259 is that the data is

double buffered. This means that the outputs DB0–DB7

will stay valid until updated at the end of the next

conversion and will not become invalid when the next

conversion starts. This facilitates interfacing with external

logic of µP.

The signal OE drives the data bus, DB0–DB7, into the

high impedance state when held low. This allows the

ML2252 and ML2259 to be tied directly to a µP system

bus without any latches or buffers.

1.7.1 Restart During Conversion

If the A/D is restarted (start goes low and returns high)

during a convesion, the converter is reset and a new

conversion is started. The output data latch is not updated

if the conversion in process is not allowed to be

completed. EOC will remain low and the output data

latch is not updated.

1.7.2 Continuous Conversions

In the free-running, continuous conversion mode, the start

input is tied to the (figure 7) EOC output. An initialization

pulse, following power-up, of mementarily forcing a logic

high level is required to guarantee operation.

Figure 8. Protecting the Input

Figure 9. Operating with Ratiometric Transducers 15% of

2.0 TYPICAL APPLICATIONS

Figure 7. Continuous Conversion Mode

START

EOC

ML2252

ML2259

START

+

–

600

Ω

GND

ANALOG

IN

ML2252

ML2259

10

µF

+

CH

ML2252

ML2259

10

µF

+

20k

3k

XDR

+VREF

+

–

4k

1k

24k

+

–

FS

ADJ

ZERO ADJ

1k